HACK: arm: dra7: clockdomain data: Fix DCAN1 RAMINIT

The DCAN1 RAMINIT mechanism doesn't work with L4CFG clock domain
in HW_AUTO, so prevent it from auto sleeping.

While being at that we also enable the CLKDM_CAN_DISABLE_AUTO for
WKUPAON clock domain as we are allowed to disable auto sleep on that
domain.

Signed-off-by: Roger Quadros <rogerq@ti.com>
HACK: arm: dra7: clockdomain data: Fix DCAN2 RAMINIT

DCAN2 RAMINIT mechanism doesn't work when L4PER2 clock domain
is set to HW_AUTO sleep. Prevent it from auto sleeping.

Signed-off-by: Roger Quadros <rogerq@ti.com>
net: can: c_can: Fix DRA7xx RAMINIT start sequence

Both DRA7xx ES1.0 and ES1.1 need a software pulse to be
created at the RAMINIT.start bit to start the RAMINIT
sequence.

It doesn't matter if interrupts are kept disabled for both
ES1.0 and ES1.1 to meet the timing requirements for ES1.0
(Errata i841).

Signed-off-by: Roger Quadros <rogerq@ti.com>
net: can: c_can: Check for RAMINIT.done on DRA7xx

Check if the RAMINIT.done bit was set after starting the RAMINIT
sequence. If it wasn't set within a certain time then print
an error message.

We are assuming here that RAMINIT.done bit must be set within
100uS of pulsing the RAMINIT.start bit.

Signed-off-by: Roger Quadros <rogerq@ti.com>