SVM related MSR registers and bitfield definitions.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
Macros, bitmasks and structs that describe the SVM virtual machine control
block aka VMCB.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
Provide functions to manipulate the guest state in the VMCB.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
Add a Cliff Notes version of the purpose and contents of the VMCB.

Requested by:	julian
- SVM nested paging support
- Define data structures to contain the SVM vcpu context
- Define data structures to contain guest and host software context
- Change license in vmcb.h and vmcb.c to remove references to NetApp that
  inadvertently sneaked in when the license text was copied from amdv.c.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
IFC @ r254014
Handle VM_PROT_NONE in nested page table code.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
HLT_IGNORED stat is used by both vmx and svm -  move to common stats.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
Add in last remaining files to get AMD-SVM operational.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
IFC @ r255692

Comment out IA32_MISC_ENABLE MSR access - this doesn't exist on AMD.
Need to sort out how arch-specific MSRs will be handled.
Revert spurious RCSID change, reducing diff against head.

Approved by:	grehan
Fix SVM handling of ASTPENDING, which manifested as a
hang on console output (due to a missing interrupt).

SVM does exit processing and then handles ASTPENDING which
overwrites the already handled SVM exit cause and corrupts
virtual machine state. For example, if the SVM exit was due to
an I/O port access but the main loop detected an ASTPENDING,
the exit would be processed as ASTPENDING and leave the
device (e.g. emulated UART) for that I/O port in bad state.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
Reviewed by:	grehan
The ASID allocation in SVM is incorrect because it allocates a single ASID for
all vcpus belonging to a guest. This means that when different vcpus belonging
to the same guest are executing on the same host cpu there may be "leakage"
in the mappings created by one vcpu to another.

The proper fix for this is being worked on and will be committed shortly.

In the meantime workaround this bug by flushing the guest TLB entries on every
VM entry.

Submitted by:	Anish Gupta (akgupt3@gmail.com)
MFC @ r256071

This is just prior to the bhyve_npt_pmap import so will allow
just the change to be merged for easier debug.
MFC @ r256071

This is the change where the bhyve_npt_pmap branch was
merged in to head.

The SVM changes to work with this will be in a follow-on
submit.
Enable memory overcommit for AMD processors.

 - No emulation of A/D bits is required since AMD-V RVI
supports A/D bits.
 - Enable pmap PT_RVI support(w/o PAT) which is required for
memory over-commit support.
 - Other minor fixes:
 * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while
delivering an interrupt, EXITINTINFO has all the details that bhyve
needs to inject the same interrupt.
 * SVM h/w decode assist code was incomplete - removed for now.
 * Some minor code clean-up (more coming).

Submitted by:	Anish Gupta (akgupt3@gmail.com)
MFC @ r259205 in preparation for some SVM updates.
Roll back botched partial MFC :(
MFC @ r259205 in preparation for some SVM updates. (for real this time)
Changes to the SVM code to bring it up to r259205

 - Convert VMM_CTR to VCPU_CTR KTR macros
 - Special handling of halt, save rflags for VMM layer to emulate
   halt for vcpu(sleep to be awakened by interrupt or stop it)
 - Cleanup of RVI exit handling code

Submitted by:	Anish Gupta (akgupt3@gmail.com)
Reviewed by:	grehan