some more work
more changes to use FPGA memory -- need to combine with fpga git repo somehow
initial transition to FPGA
Back to the future.  Reboot to using the SPI interface between micro and rest of the system.  Using external SRAM for the ROM and non-FDC register locations.  Giving up on the standalone CPLD-based solution, at least until I have an FDC setup that works for both DECB and NOS9.  The writing is much easier to construct and doesn't seem to have a significant impact on the performance, though I still need to test the interrupt handlers.