[AArch64] Enabled AA support for Cortex-A53.

Patch by Sanjin Sijaric <ssijaric@codeaurora.org>!
Phabricator Review: http://reviews.llvm.org/D5103

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217370 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Improve AA to remove unneeded edges in the AA MI scheduling graph.

Patch by Sanjin Sijaric <ssijaric@codeaurora.org>!
Phabricator Review: http://reviews.llvm.org/D5103

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217371 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add InstrMapping for noret atomics.

Only handles LDS atomics for now, and will be used
to replace atomics with no uses with the no return
versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217378 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Replace LDS atomics with no return versions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217379 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix assertion from copying a TargetGlobalAddress

Assert in scheduler from an inserted copy_to_regclass from
a constant.

This only seems to break sometimes when a constant initializer
address is forced into VGPRs in a non-entry block. No test
since the only case I've managed to hit only happens with a future
patch, and that case will also not be a problem once scalar instructions
are used in non-entry blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217380 91177308-0d34-0410-b5e6-96231b3b80d8