tegra: pmc: add command to get into RCM

In RCM aka recovery mode the BootROM waits for a
usbloader to take over control. On most boards this
is triggered by holding a physical switch which may
be inconvinient at times. Add a command to switch
into RCM from software.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: lowlevel: setup an early stack

Even the lowlevel functions are growing to a
size where having a stack seem beneficial.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: add Tegra124 id to lowlevel functions

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: lowlevel: fix ODMdata fetch on Tegra124

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: recognize Tegra124 in maincomplex startup

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: recognize Tegra124 in common initcalls

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: disable IDDQ for PLL_X on Tegra124

This is an additional power down control.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: power up additional partitions on Tegra124

Those 3 are needed to power CPU0 from the CPUG cluster.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: fix MESLECT clock enable

Don't disable clk to unrelated devices in the process.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: change cpu internal reset layout for Tegra124

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: add Tegra124 PLL_X rate setup

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: apply cluster switch logic to all SoCs >=T30

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: hardcode entry address for main cluster

I don't know why get_runtime_offset fails on T124 yet,
but this is a safe workaround, with the nice side-effect
of fixing second stage barebox loading.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: setup L2 cache on Tegra124

Set SRAM latency to 3 clock cycles.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: add architectural timer init

If the bootloader doesn't init the architectural timer
on Cortex A15 Linux falls over when trying to boot.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tegra: add Tegra124 Kconfig symbol

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
pinctrl: tegra30: introduce drvdata

Access pin and drivegroups through a drvdata pointer.
This allows to insert other groups for SoCs with a
similar bit layout easily.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
pinctrl: tegra: add Tegra124 support

We can reuse the Tegra30 pinctrl driver, as the bit
layout is the same. Just add the pin and drivegroups
and some compile-time magic to avoid bloat.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
clk: tegra: allow variable sized muxes

Tegra124 extended the mux by 1bit to allow for
more PLL sources.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>