usb: gadget: midi: Fix ignored "index" and "id" module parameters

The MIDI USB gadget driver has "index" and "id" parameters which should
determine the alsa sound card index and id to use when registering the
card. Those parameters had no effect, as the relevant information is only
set on the midi structure after f_midi_register_card is called.

This patch moves the two initialisation statements before the function call.

Signed-off-by: Marcus Weseloh <marcus@weseloh.cc>
sun4i-keyboard: 250Hz LRADC sampling

This is required to have fast enough key presses with sun4i-keyboard
(actually used on sun4i, sun5i and sun7i) on CWM recovery, an Android
initramfs that allows easy flashing of the devices. With any lower
sampling rate, close key presses are not distinguished and reported
as one long press.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
sunxi: axp209: Protect dcdc3 voltage from modification

The dcdc3 voltage is expected to be set by the bootloader and the right
voltage depends on the DRAM settings (higher clock speed needs more
voltage). Allowing to use the 'dcdc3_vol' parameter from the FEX file
only introduces an unnecessary fragile dependency between the settings
in u-boot and the settings in FEX. So now we ignore this parameter in
FEX and keep the original dcdc3 voltage set by the bootloader.

The dmesg log now looks like this:

[    2.212941] axp20_ldo1: 1300 mV
[    2.221370] axp20_ldo2: 1800 <--> 3300 mV at 3000 mV
[    2.231662] axp20_ldo3: 700 <--> 3500 mV at 2800 mV
[    2.241747] axp20_ldo4: 1250 <--> 3300 mV at 2800 mV
[    2.251906] axp20_buck2: 700 <--> 2275 mV at 1400 mV
[    2.263430] somebody is trying to set dcdc3 range to (1300000, 1300000) uV
[    2.275327] but we keep dcdc3 = 1250000 uV from the bootloader
[    2.285406] axp20_buck3: 700 <--> 3500 mV at 1250 mV
[    2.295299] axp20_ldoio0: 1800 <--> 3300 mV at 2800 mV

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
sunxi: Calculate PLL5P clock divisors for G2D, ACE and DEBE

When PLL5P is used as a parent clock for some of the peripherals,
the current code just selects some hardcoded divisors. This happens
to work, but only under assumption that the PLL5P clock speed is
somewhere between 360MHz and 480MHz (the typical DRAM clock speeds).

However with some tweaks for the DRAM parameters, it is possible to
clock DRAM up to 600MHz and more on some devices:

    http://lists.denx.de/pipermail/u-boot/2014-July/183981.html

And this introduces concerns about the hardcoded divisors in the
kernel, which may cause some peripherals to operate at abnormally
high clock speeds if the PLL5 clock speed is too fast (PLL5 is used
for clocking DRAM).

Moreover, it makes sense to avoid pre-dividing PLL5P and make it run
even faster than DRAM. This provides better granularity of the clock
speed selection for MBUS, G2D and everything else that is using PLL5P
as the parent clock. but running PLL5P faster means that the hardcoded
divisors become even more inappropriate.

This patch improves the clock divisors selection for G2D, ACE and
DEBE to insure that they can work correctly with any PLL5P clock
speed.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>