clk: sunxi: Add support for sun9i a80 usb clocks and resets

The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller.

This patch copies the original gates clk functions used for usb
clocks into a separate file, and renames them to *_usb_*. Also
add a per-gate parent index, so we can set different parents for
each gate.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun9i: Add usb clock nodes to a80 dtsi

The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
phy: Add driver to support individual USB PHYs on sun9i

Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.

This adds a new driver to support the regular USB PHYs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun9i: Add usb phy nodes to a80 dtsi

On sun9i, there are 3 independent usb phys. Add device nodes for them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun9i: Add USB host controller nodes to a80 dtsi

The A80 has 3 EHCI/OHCI USB controllers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun9i: Enable USB support on A80 Optimus board

Signed-off-by: Chen-Yu Tsai <wens@csie.org>