Change how levels are set
Merge branch 'master' of github.com:psi46/pxar
Merge to Head
Removed Setting basee on TBM Core B to non zero
Switched to using the i2c addresses from the enabled ROCs list
Merge pull request #228 from psi46/ethernet_interface

Ethernet interface
Bump version to 1.7.0: merged CMake changes including some first
code for a future Ethernet interface.
Merge pull request #259 from drberry85/master

Timing Test Update
Readback test: ready for module data handling, functionality (re-)verified on single ROC
add module test script
Merge branch 'master' of github.com:psi46/pxar
make it compile (uint is not allowed!)
Update PixTestTiming.cc

Comment out level scan from timing test until firmware issue is addressed. This is a response to issue #261.
Merge pull request #262 from drberry85/patch-1

Update PixTestTiming.cc
FIRMWARE UPDATE to 3.5: this updates the RPC interface to allow
access of the slow ADC readbacks from single ROC platines:
VD_Reg, VDAC_Reg, VD_Cap. Version bumped to 1.7.1
check against flawed readout
Merge branch 'master' of github.com:psi46/pxar
corrections to cross check
corrections to cross check
remove strict requirement on NO errors for trimming
more protections and correcting wrong /3