[dev][timer][cortex-a9] do not allow ticks of 0 to be set

-Make sure tick values passed in are within valid range of hardware.
[platform][zynq] set memory map of AXI busses to device mode
[lib][fixed_point] move fixed point routines into a separate library
[dev][timer][cortex_a9] move timer to fixed point divide routines
[app][clock_tests] handle having current_time() divides round properly

This will probably break implementations that truncate round.
[pktbuf] Fix NULL deref when the freelist is empty
[zynq] Fix bug forcing 32bit ddr width when coming out of reset
[zynq][gem] Move MIO cfg in the gem driver to the target cfg
[zynq][gem] Add ETH1 support
[zynq] Setup eth1 clocks
[zynq][gem] Move uzed and zybo gem inits to target
[platform][zynq] detect flash in single spi mode and add command to set qspi mode

Change-Id: I3d0ea403c79f9b7a8c34c9f871e97bd728b46d7f
[zynq][qspi] properly remember the current speed setting

-this was causing the spiflash driver to drop to 50mhz and never go back to 100

Change-Id: If231f5b0281b17001abfbafd50afa9eb8a7a77cb
[zynq][spiflash] write enable before using the cr1 write routine

Change-Id: Id3dbffee2438bfca3208884b4a46cffeb79eccf2
[zynq][spiflash] wait a bit before rereading cr1 register

Change-Id: Ie791fb689f9c2bac9127ae27ac3a83274f67755a
[arch][arm] fix cache flush routines to pass proper address to pl310

-add another sync in a few of the pl310 routines
[arch][arm] add back the bottom bits in the returned address of arm_vtop()
[platform][zynq][gem] put the GEM driver in cached mode

Add appropriate flushing for the TX and RX path
[app][tests] beef up the cache benchmark tests a little bit
[dev][cache][pl310] r2+ versions of the pl310 do not require waiting for ops by PA