Add a feature flag for slow 32-byte unaligned memory accesses [x86].

This patch adds a feature flag to avoid unaligned 32-byte load/store AVX codegen
for Sandy Bridge and Ivy Bridge. There is no functionality change intended for 
those chips. Previously, the absence of AVX2 was being used as a proxy to detect
this feature. But that hindered codegen for AVX-enabled AMD chips such as btver2
that do not have the 32-byte unaligned access slowdown.

Performance measurements are included in PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ).

Differential Revision: http://reviews.llvm.org/D6355



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Fix formatting. NFC.

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Less space; NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222546 91177308-0d34-0410-b5e6-96231b3b80d8
Allow multiple -debug-only args

Debug output is shown if any of the -debug-only arguments match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222547 91177308-0d34-0410-b5e6-96231b3b80d8