BFQ : inline with DirtyV
Magic Ramspeed for Tuna ;-)

 Enable SCU Speculative linefills

By enabling SCU Speculative linefills in the SCU Control
Register, the  L2 cache access latency seems tp be reduced
a bit with an overall ~1.5% improvement.

 Tuna: set PL310 cache controller prefetch offset to 3

Now that double linefill is enabled the PL310 prefetch
offset needs re-evaluation. Benchmarks show that value
of 3 (or 4, close second) is the optimal value.

Performance gains in memory bandwidth tests up to 9%.

RgBandwidth (Threads: Auto, Test: Misc)

Copy   1826.6 MB/s  ->  1915.8 MB/s
Scale  1672.2 MB/s  ->  1812.7 MB/s
Add    1778.9 MB/s  ->  1905.3 MB/s
Triad  1746.2 MB/s  ->  1844.7 MS/s

 Enable PL310 double linefill for Tuna board

Double linefill was disabled because of single cache line
corruption in first revisions of OMAP 4460. On Tuna board,
after extensive testing, no cache corruption cases were
observed.

Benchmarks (RgBandwidth, Antutu) show up to 45% performance
gains in memory bandwidth tests.

RgBandwidth (Threads: Auto, Test: Misc)

     Single Linefill   Double Linefill

Copy   1403.0 MB/s  ->  1826.6 MB/s
Scale  1386.8 MB/s  ->  1672.2 MB/s
Add    1227.7 MB/s  ->  1778.9 MB/s
Triad  1225.3 MB/s  ->  1746.2 MB/s
 OMAP4: do not force workarounds for errata fixed in 4460

Signed-off-by: Mans Rullgard <mans.rullgard at linaro.org>
ARM: OMAP4: l2x0: Cleanup prefetch offset register setting