Reconfigured hardware to include USER data area

1. SRAM_Controller now uses byte enable and completes in 1 cycle less

2. timing enhancements to the control unit
2.1. use registered NOS for memory bus data output channel
2.2. avoid using equalzero on the unregistered value of TOS to select state_n
with ?dup and THROW, rather make the necessary decision on the second cycle with a registered value

3  included 32 VM * 2K USER RAM blocks
3.1. a temporary hardware register is used to select the VM no.

Tested in simulation and on the Nexys board