Introduce basic support for ARM64 CPU affinity

CPU affinity fields declared in MPIDR_EL1 describe
four affinity levels for each CPU core in the system creating
unique CPU address: <Aff3>.<Aff2>.<Aff1>.<Aff0>
Introduce __cpu_affinity[] array indexed by CPU number as seen
by the system and accessor macro cpu_affinity().
Current implementation supports only single CPU cluster which means
that only Aff0 is expected to change whereas Aff3-Aff1 are expected
to stay unchanged.
Use already defined CPU functions and macros to extract pcpu pointer

Since there are get_mpidr() and CPU_AFF() we can use them
to minimize code redefinitons and link related data
structures for future development (SMP).
Fix some obvious mistakes in ARM PL011 UART

- Don't forget uart_barrier() on write.
- After disabling UART, wait for transmission to finish before
  changing control and line. Timeout and fail if something's wrong
  with the hardware.
- Check for break and overrun only on RX.
- Change masking of TXEMPTY interrupt to clearing it as this was
  the original intention.
Add 64KB page definitions for ARM64
Introduce basic support for ARM Generic Interrupts Controller v3.0

- Enable GIC CPU interface access via system registers in locore.
  The necessary configuration is performed in EL2.
- Add preliminary GICv3 driver:
  - distributor, re-distributo and CPU interface configuration
  - basic interrupts handling (PPIs and SPIs only)

- Missing bits:
  - "redistributor-regions" support
  - SGI support
  - ITS
  - selected interrupt configuration (pic_config method)
Add CPU part name for Cavium Thunder

Name selected according to DTS description for "cpu" node.
Improve ARM64 CPU identification.

- Keep CPU description per-CPU (indexed by cpuid)
- Rework Implementer/PartNum relation
  - need to have separate PartNum tables for each implementer