PowerPC: Optimized isnan/isnanf for POWER8

This patch add a optimized isnan/isnanf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport of 487972aea52004f604c2878c8c9d3e77670f2c32
PowerPC: Optimized isinf/isinff for POWER8

This patch add a optimized isinf/isinff implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport of 4393fc119c34e97519b9b7a4fc94066b283be452
PowerPC: Optimized finite/finitef for POWER8

This patch add a optimized finite/finitef implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport of cac626d60a863e48ab75417064984769e58c5719.
PowerPC: llrint/llrintf POWER8 optimization

This patch add a optimized llrint/llrintf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport of 1ad8950a3ea4056ed343d681b5146f4b4aa27e10
PowerPC: llround/llroundf POWER8 optimization

This patch add a optimized llround/llroundf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport fe13a20c37578f08ce393ccaeb45caeb48815ca5
PowerPC: strrchr optimization for POWER7/PPC64

This patch optimizes strrchr() for ppc64. It uses aligned memory
access along with cmpb instruction and CPU prefetch to avoid
cache misses for speed improvement.

Backport of c7debbdfacbef150aaf9113eb05ccaf2b9e7af6c