Support for addnuw and addnw instruction

addnuw is implemented by verifying that the result of two operands
is always greater than or equal to both operands.

addnw is for Add No Wrap, which is invoked when both NSW and NUW
flags are enabled.

Note: addnuw can also be implemented by zero extending both the operands,
computing the sum of two and verifying if the N+1th bit is 1, which means
undefined behavior. Not sure which of the two appraoches for addnuw would
be faster? I will submit it as next patch.
Modified addnuw inst implementatin patch by code refactoring

To avoid rewriting the same piece of code twice in AddNUW and
AddNW instruction implementation, define function to implement
addnuw instruction.
Support for subnuw and subnw instruction

subnuw is implemented by verifying that the difference of two
operands is always less than or equal to first operand. This
can also be implemented by zero extending both the operands and
then verifying the N+1th bit of the computed diff. If its 1, then
its an undefined behavior, otherwise not.
Support for multiplication instruction

Categorized the instruction as MulNSW, MulNUW and MulNW. The basic
idea is to sign/zero extend the operands original width to double.
Compute the producct and then truncate it to original width. Compare the
product (of extended operands) and extended Truncated value. If its
not same, then its an undefined behavior.

MulNW is for the case when both NSW and NUW flags are enabled. In this
case, we check both the conditions.
Added conditions to verify div and rem instruction

Added the checkpoints to verify the undefined behavior in division and remainder
instructions. Also, added the support for exact division. The key idea is to
verify that the result of division is not rounded. Simple check is:
Quotient(Result) * Divisor(Opd2) = Dividend(Opd1)
and the Divisor is always non zero.
Assertions for shift op and support nsw, nuw and exact shift operation

Added check points to verify such that shift operation does not give
undefined behavior. Asserted that the number of bits by which the left
operand has to be shifted must be always smaller than the width of the
left operand. Also, added support for nsw, nuw by shifting logically and
arithmetically respectively. Exact shift is asserted such that the right
shifted result if shifted left by same number of bits, must give the
original left operand.
Fixed mul instruction and added test cases

Fixed the width issue in mul op. Added test cases in extractor test
for addnuw and udiv. But, these don't seem to be integrated well
right now.