msm: vidc: Validate userspace buffer count

Makesure the number of buffers count is less than
the maximum limit to avoid structure overflow errors.

Change-Id: Icf3850de36325637ae43ac95f1c8f0f63e201d31
CRs-fixed: 563694
Signed-off-by: Pachika, Vikas Reddy <vpachi@codeaurora.org>
msm: vidc: Validate userspace buffer count before using it

Validate the number of buffers count variable before
using it to avoid structure overflow error.

Change-Id: I61582c93e0f26ec6842e437134fb8a42bdbc36ff
CRs-fixed: 563654
Signed-off-by: Pachika, Vikas Reddy <vpachi@codeaurora.org>
Merge "msm: vidc: Validate userspace buffer count before using it"
Merge "msm: vidc: Validate userspace buffer count"
msm: ocmem: Call restore_sec_config() after every power collapse

As the QRIB is enabled, after every power collapse of ocmem, the
QRIB is reset to the maximum security state. Due to this the apps
processor cannot access the ocmem register space.

The restore_sec_config() scm call needs to be called before any
register is accessed after a power collapse to ensure that the
security configuration is restored. The clocks need to be turned
on before every call that is made into TZ to ensure that there
is no power collapse.

CRs-Fixed: 651324, 660089
Change-Id: Ieb6b635142057e219de29e811c93749f6500cec5
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Merge "msm: ocmem: Call restore_sec_config() after every power collapse"
msm: kgsl: Enable protected mode for A3XX

Enable protected register mode for A3XX with these commits from
msm-3.10:

msm: kgsl: Enable protected register mode for A3XX
msm: kgsl: Print the register that causes a protected mode error
msm: kgsl: Unprotect the VBIF performance counters

Change-Id: Ic0dedbad950ffbd063fd861d9440bb5dce8d5fb1
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Protect SMMU registers from being written by the GPU

Put the SMMU register range in protected mode to shield them from
IB1/IB2 writes from userspace.

CRs-Fixed: 599971
Change-Id: Ic0dedbad8c03fc1c54ff73221231e2440d3c34dd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Protect CP_STATE_DEBUG_INDEX

Put CP_STATE_DEBUG_INDEX and CP_STATE_DEBUG_DATA under protection
to keep it from being written from an IB1. Doing so however opens
up a subtle "feature" in the microcode: memory read opcodes turn off
protected mode in the microcode to do the read and then turns it
back on regardless of the initial state. This is a problem if the
memory read happens while protected mode is turned off and then we
try to access a protected register which then complains and goes boom.

To account for this irregularity explicitly turn back off protected
mode in all the places where we know this will be a problem.

Change-Id: Ic0dedbad1397ca9b80132241ac006560a615e042
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Merge "msm: kgsl: Enable protected mode for A3XX"
Merge "msm: kgsl: Protect SMMU registers from being written by the GPU"
arm: mach-msm: Remove the unused rmt_storage code

The rmt_storage module is no longer used.
Remove the unused module and cleanup the makefile and kconfig.

CRs-Fixed: 549951
Change-Id: Ie9ebaa2209ea9fa0df05dc892504fcb882f00f29
Signed-off-by: Nikhilesh Reddy <reddyn@codeaurora.org>
Merge "msm: kgsl: Protect CP_STATE_DEBUG_INDEX"
Merge "arm: mach-msm: Remove the unused rmt_storage code"
arm: msm: acpuclock-8226:  Add support for 1.1GHz for 8610

Add a new frequency table for 1.1GHz parts for speed-bin 1.

Change-Id: I4df8ae9f14e0c1444f3a96d065c93f6cfcd0243b
Signed-off-by: Taniya Das <tdas@codeaurora.org>
ARM: msm: dts: Add efuse register base for 1.1GHz

New efuse base register has been added to support new speed bin of
1.1GHz.

Change-Id: I71d278d05a0f936baa70b0f5f41da7df83910bc7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
msm: thermal: Add support for cpu temp limit recommendation for SoC

Add support in KTM to get SoC parts info by reading appropriate
efuse bits and recommend default cpu temperature limit based on
efuse value temperature map to userspace through sysfs interface
'/sys/module/msm_thermal/default_cpu_temp_limit'. Efuse data
to be read such as address, row number, starting bit number
of the row, number of bits for identifying parts etc, default core
temperature and efuse temperature value map are read from dt.
The default cpu temperature information is exported in the format
<temperature in degree celsius>.

Change-Id: Icbf43c3fd56e95d49a886d309e613d2fe146a506
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
ARM: dts: msm: Add default cpu temp limit info entry for MSM8610

Add efuse data for identifying SoC parts and cpu temperature limit
information for different parts to thermal for MSM8610.

Change-Id: I1b50280c7c8092544165b26b95e235e5571a63d3
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Merge "arm: msm: acpuclock-8226:  Add support for 1.1GHz for 8610"
Merge "ARM: msm: dts: Add efuse register base for 1.1GHz"