FogBugz #177545: Remove the need to force the USB IP into Host mode

Users must correctly use a USB OTG A-mini to A Male cable adapter and the USB
IP will correctly transistion into HOST mode.

Re-align the DWC2 USB driver with kernel.org.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
FogBugz #176300: Add support for multiple clock parents

The periph and sdram PLL can have any of 3 parents. For the perip pll, the
parents can be either: osc1, osc2, or f2s_periph_ref_clk. For the sdram pll,
the parents can be: osc1, osc2, or f2s_sdram_ref_clk.

Update the clock driver to read the appropriate register for determine the
correct parent for the periph and sdram PLL.

Add the new clock entries into the socfpga DTSI file. Also remove the
"clock-frequency" property for the f2s_periph_ref_clk from the DTSI file, as
this property should be in the DTS file.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
FogBugz #172665: Sample driver for DMA transfer to FPGA soft IP (FIFO)

-This fpga-dma driver is an example driver for a specific FPGA soft IP
-The soft IP presents a FIFO which can be read and written through
the debugfs interface
-The DMA transfer code uses 'generic' dma interfaces
-The fpga-dma driver uses generic register and DMA definitions
in the devicetree

V2:
-Device tree changes removed from socfpga_cyclone5.dts and
documented in Documentation/devicetree/bindings/arm/altera/fpga-dma.txt

V3:
-Formatting changes, used Lindent script to format fpga-dma.c

V4:
-More formatting changes, lined up #defines, alphabetize headers

Signed-off-by: Graham Moore <grmoore@altera.com>
FogBugz #178128: Conditionally enable L2 EDAC.

Currently the L2 cache is the only ECC module implemented in
the ECC Manager. However, as more modules are added, the need
to turn each module on & off is required. The addition of
conditional compiles based on a new CONFIG (L2 ECC) is added
here.

V2:
Include dependency on CONFIG_CACHE_L2X0

Signed-off-by: Thor Thayer <tthayer@altera.com>
FogBugz #173185: OCRAM ECC addition for Altera SOCFPGA.

Add On-Chip RAM ECC to the Error Detection And Correction module for
tracking ECC errors in Altera's SOCFPGA OCRAM.
This patch adds code to the kernel startup that initializes OCRAM
and ensures the ECC is enabled. The generic EDAC Manager driver
handles the addition of OCRAM to the driver when the OCRAM "compatible"
field in the device tree matches.
Specific data is loaded depending upon which type of ECC (L2 or OCRAM)
is being initalized.

V2 Changes:
- Fix error message in OCRAM initialization.
- Document the device tree bindings for OCRAM & OCRAM ECC.
- Change variable name from sram to iram for clarity.
- Resync with main since EDAC L2 trigger was added.

V3 Changes:
- Remove OCRAM device tree binding file.
- Add conditional compile statements for L2 clear in socfpga.c

V4 Changes:
- Add OCRAM only config.
- Split OCRAM initialization into own files (ocram.c & ocram.h)
- Conditionally compile OCRAM matching tag.

V5 Changes:
- Cleanup of ocramedac address in socfpga.dtsi
- Use pr_err() consistently in ocram.c

V6 Changes:
- Cleanup of ocramedac address in socfpga-ocram-ecc.txt.
- Remove unused .setup function pointer.

Signed-off-by: Thor Thayer <tthayer@altera.com>
ARM: socfpga: dts: fix s2f_* clock name

The s2f_* clocks are called h2f_* in the datasheets.
Rename them accordingly in the socfpga.dtsi.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>

Conflicts:

	arch/arm/boot/dts/socfpga.dtsi