i965/fs: Allow CSE on math opcodes on Gen6+.

total instructions in shared programs: 2081469 -> 2081248 (-0.01%)
instructions in affected programs:     22606 -> 22385 (-0.98%)
No programs were hurt by this patch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Don't set the "switch" flag on control flow instructions on Gen6+.

Thread switching on control flow instructions is a documented workaround
for Gen4-5 errata.  As far as I can tell, it hasn't been needed since
Sandybridge.  Thread switching is not free, so in theory this may help
performance slightly.

Flow control instructions with the "switch" flag cannot be compacted, so
removing it will make these instructions compactable.  (Of course, we
still have to implement compaction for flow control instructions...)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Make src_reg::equals() take a constant reference, not a pointer.

This is more typical C++ style.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
i965: Split Gen4-5 and Gen6+ MATH instruction emitters.

Our existing functions, brw_math and brw_math2, had unclear roles:

Gen4-5 used brw_math for both unary and binary math functions; it never
used brw_math2.  Since operands are already in message registers, this
is reasonable.

Gen6+ used brw_math for unary math functions, and brw_math2 for binary
math functions, duplicating a lot of code.  The only real difference was
that brw_math used brw_null_reg() for src1.

This patch improves brw_math2's assertions to allow both unary and
binary operations, renames it to gen6_math(), and drops the Gen6+ code
out of brw_math().

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965: Rename brw_math to gen4_math.

Usually, I try to use "brw" for functions that apply to all generations,
and "gen4" for dead end/legacy code that is only used on Gen4-5.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/vec4: Drop the generate_math2_gen7() method.

It's now a single line of code, so we may as well fold it into the
caller.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/vec4: Combine generate_math[12]_gen6 methods.

These are trivial to combine: we should just avoid checking the second
operand if it's brw_null_reg.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Drop the generate_math[12]_gen7 methods.

These functions are basically identical, so we should combine them.
However, they're so trivial, we may as well just fold them into their
only call sites.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Combine generate_math[12]_gen6 methods.

These used to call different math emitters (brw_math vs. brw_math2).
Now that they both call gen6_math, they're virtually identical.

When unrolling SIMD16 to multiple SIMD8 operations, we should take care
not to apply sechalf to brw_null_reg for src1.  Otherwise, we'd end up
with BRW_ARF_NULL + 1 as the register number, and I'm not sure if that's
valid.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
meta: Label the meta GLSL clear program.

Giving the meta clear program a meaningful name makes it easier to find
in output such as INTEL_DEBUG=fs or INTEL_DEBUG=shader_time.  We already
did so for integer programs, but neglected to label the primary program.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Don't use the head sentinel as an fs_inst in Gen4 workaround code.

When walking backwards, we want to stop at the head sentinel, which is
where scan_inst->prev->prev == NULL, not scan_inst->prev == NULL.

Fixes random crashes, as well as valgrind errors.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
i965: Invalidate live intervals when inserting Gen4 SEND workarounds.

We need to invalidate the live intervals when inserting new
instructions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
i965: Add GPU BLIT of texture image to PBO in Intel driver

Add Intel driver hook for glGetTexImage to accelerate the case of reading
texture image into a PBO.  This case gets huge performance gains by using
GPU BLIT directly to PBO rather than GPU BLIT to temporary texture followed
by memcpy.

No regressions on Piglit tests  with Intel driver.
Performance gain (1280 x 800 FBO, Ivybridge):
glGetTexImage + glMapBufferRange  with patch 1.45 msec
glGetTexImage + glMapBufferRange without patch 4.68 msec

v3: (by Kenneth Graunke)
 - Fix compile after Eric's change to drop the tiling argument
   to intel_miptree_create_for_bo.
 - Add GL_TEXTURE_3D to blacklisted texture targets to prevent Piglit
   regressions.
 - Squash in several whitespace and coding style fixes.
tgsi/gs: bound max output vertices in shader

This limits the number of emitted vertices to the shaders max output
vertices, and avoids us writing things into memory that isn't big
enough for it.

Reviewed-by: Zack Rusin <zackr@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
softpipe: add depth clamping support. (v2)

This passes the piglit depth clamp tests.

this is required for GL 3.2.

v2: move min/max up one level, could go further, thanks
to Roland for suggestion.

v1: Reviewed-by: Brian Paul <brianp@vmware.com>

Signed-off-by: Dave Airlie <airlied@redhat.com>
softpipe: add layering to the surface tile cache.

This adds the layer info to the tile cache.

This changes clear_flags to be dynamically allocated as
MAX_LAYERS seems like a too big step.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
softpipe: add layered rendering support.

This adds support for GL 3.2 layered rendering to softpipe.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
tgsi_exec: use defines for max inputs/outputs

This fixes the limits for GL 3.2, and subsequently fixes
some segfaults in some varying packing tests and max varying tests
after the limits bumped.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
softpipe: bump the softpipe geometry limits

This just aligns the limits with llvmpipe.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
softpipe: enable GLSL 3.30 support.

This enables GL3.3 on softpipe.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>