x86: Setup correct TSL/TR segment attributes on INIT

The TSL & TR segments didn't contain valid attributes. This caused
problems when transfering the state into KVM, where invalid state
means no-go. Fixup the attributes with values from AMD's architecure
programmer's manual.
x86: Set CS limit to 0xffff on INIT

It seems like gem5 used to store segments limits as the actual limit
in memory (x86 stores the segment size). However, the ISA code doesn't
seem to do the necessary calculations, so in practice, we seem to
store the size of the segment rather than size+base. This changeset
changes the CS limit to exclude the base of the segment when
initialized by the INIT interrupt.