or1200-generic: add debug tap anf jtag_vpi support

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add csrbrg core
cores: add minimac2 core
Merge branch 'minimac2' of https://github.com/veprbl/orpsoc-cores into upstream
verilator_tb_utils: add a JTAG server for OpenOCD

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
or1200-generic: use jtagServer from verilator_tb_utils

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
systems/atlys: set MMU sets to 128

There's room for the extra logic/RAM resources this takes,
so no reason to skimp on it.
mor1kx-generic: add debug tap and jtag server support

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
atlys/clkgen: remove defparams
atlys: remove invalid DIVIDE(2) on BUFIO

Newer ISE (reported on >= 14.5) fail to build designs with
BUFIO2 that has the DIVIDE parameter set to 2.
The error message is:
"ERROR:PhysDesignRules:2502 - Issue with pin connections and/or
configuration on
   block:<dvi_gen0/sysclk_div>:<BUFIO2_BUFIO2>.  BUFIO2 has an invalid
setting
   of DIVIDE by 2. This setting is not supported. For more information
please
   see Answer Record 56113.
ERROR:Pack:1642 - Errors in physical DRC."

And, Answer Record 56113 states the following:
"In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can
occasionally enter a stuck state. Hence, it is not supported and an
alternative implementation needs to be used."

To get around this, instead of feeding the 100 MHz system clock
into dvi_gen, an already divided by 2 50MHz clock is used.
atlys: add timing constraints for dvi_gen CDC
wb_altera_ddr_wrapper: fix read_done CDC problems

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_altera_ddr_wrapper: fix classic wb transaction

In some circumstances there might be an unwanted wb_ack while
doing classic wishbone access.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
verilator_tb_utils: VerilatorTbUtils::doJTAG: check if jtag is enabled
mor1kx-generic: tb.cpp: check for NOP_EXIT_SILENT
cores: add cfi_ctrl from opencores

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_port_arbiter: fix cache coherency during wb block write

Multiples write can occur during a single write block cycle.

Old code triggers a buffer write on the rising edge of wb_cyc.
This only works with single write cycles.

This patch signals that a write have happend to all ports
on every wb_ack during the write block cycle.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Merge branch 'master' of https://github.com/openrisc/orpsoc-cores