winsys/radeon: Use separate caching buffer manager for each set of flags

Otherwise the caching buffer manager may return a buffer which was created
with a different set of flags, which can cause trouble.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
r600g,radeonsi: Use staging texture for transfers if any miplevel is tiled

We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU
access may not work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
r600g,radeonsi: Only set use_staging_texture = TRUE once

No need to check for setting the flag after we set it already.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
i965: Allow CSE on Gen4-5 unary math.

Due to the implicit move-from-GRF, unary math looks a lot like the Gen6+
math instruction: it's a single instruction (SEND) with a GRF source.
The difference is that it also implicitly clobbers a message register.

The only visible effect is that CSE will remove the MRF-clobbering from
later math operations.  This should be fine; compute_to_mrf and
remove_redundant_mrf_writes don't look at the values populated by
implied writes, so they can't rely on those values being present.
Less interference may actually help those passes make more progress.

Binary math is still problematic, since it involves a separate MOV
instruction to load the second operand.  We continue disallowing CSE for
binary math operations.

total instructions in shared programs: 3340303 -> 3340100 (-0.01%)
instructions in affected programs:     26927 -> 26724 (-0.75%)
Nothing hurt, gained, or lost.  ~6% reduction on a few shaders.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
vc4: Move the output semantics setup to a helper.

I want to reuse it elsewhere to set up outputs that aren't in the TGSI.
vc4: Add support for user clip plane and gl_ClipVertex.

Fixes about 15 piglit tests about interpolation and clipping.
vc4: Fix the uniform debug output.

I dropped the shader index when moving to the compiled shader struct, but
didn't update the format string here.
freedreno/a3xx: refactor vertex state emit

Get rid of fd3_vertex_buf and use fd_vertex_state directly for all
draws.  Removes a tiny bit of CPU overhead for munging around the vertex
state every time it is emitted, but more importantly it cleans things up
for later optimizations, so the emit paths don't have to special case
internal draws (gmem<->mem, clears, etc) with regular draws.

Instead of constructing fd3_vertex_buf array each time for internal
draws, and context init time pre-create solid_vbuf_state and
blit_vbuf_state.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/a3xx: refactor/optimize emit

Because we reuse various bits of emit code (for state/vertex/prog/etc)
for both regular draws and internal draws (gmem<->mem, clear, etc), the
number of parameters getting passed around has been growing.  Refactor
to group these into fd3_emit.  This simplifies fxn signatures, avoids
passing around shader key on the stack, etc.  It also gives us a nice
place to cache shader-variant lookup to avoid looking up shader variants
multiple times per draw (without having to *also* pass them around as
fxn args everywhere).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: optimize shader key comparision

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno: inline fd_draw_emit()

Manual LTO

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno: fix layer_stride

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: large const support

Signed-off-by: Rob Clark <robclark@freedesktop.org>
i965: Restore a lost comment about TXF offset bugs.

Eric's original code to work around TXF offset bugs contained a comment
explaining the problem, which was lost when Chris generalized it to an
IR transformation (in commit 598ca510b8a118c3c7e18b5d031a2b116120e0a6).

This commit adds the original comment to the newer code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Drop ir->op != ir_txf condition in offset checking.

brw_lower_unnormalized_offset sets ir->offset to NULL if it applies the
texelFetchOffset workarounds, so there's no need to special case it
here---there won't be an offset for ir_txf.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: Move texel offset handling to visit(ir_texture *).

This moves the handling of non-constant texel offset subexpression trees
to the place where we visit other such subtrees.  It also removes some
uses of ir->offset in emit_texture_gen7, which will be useful when we
write the backend for our new upcoming IR.

Based on a patch by Connor Abbott.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: don't use ir->offset in emit_texture_gen5.

v2 (Ken): Refactor the Gen7 code separately; rebase.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Make brw_texture_offset() not use ir_texture.

Our new IR won't have ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: Rename "length" to "components" in emit_mcs_fetch().

This is slightly clearer.  Based on a patch by Connor Abbott.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>