[CORE] Return more error information from vmm_vcpu_irq_wait_resume()

Currently, we are skipping lot of error scenarios while returning
from vmm_vcpu_irq_wait_resume() (i.e. vmm_vcpu_irq_wait_resume()
silently returns VMM_OK for those skipped error scenarios). If
vmm_vcpu_irq_wait_resume() returns error codes for all failure
cases then it will be helpful to the caller to do something when
vmm_vcpu_irq_wait_resume() fails.

This patch updates vmm_vcpu_irq_wait_resume() to capture more
failure cases.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Add vmm_manager_vcpu_hcpu_resched() & vmm_manager_vcpu_hcpu_func() APIs

This patch adds two new useful APIs to vmm_manager for SMP host:
1. vmm_manager_vcpu_hcpu_resched() - This API forces rescheduling on the
host CPU assigned to given VCPU.
2. vmm_manager_vcpu_hcpu_func() - This API helps us call a function on
the host CPU assigned to given VCPU.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: SGI sources and IRQ-to-LR mapping improvments

This patch does minor improvements to:
1. Per-VCPU SGI sources used to trigger SGIs: We need to
protect the per-VCPU SGI sources hence me move "sgi_sources"
from struct vgic_vcpu_state to struct vgic_guest_state and
protect it using "dist_lock".
2. Per-VCPU IRQ-to-LR mapping: Currently we only mapped
each IRQ to LR assigned to it. Instead this should be
(IRQ, Source CPU) mapped to assigned LR for capturing
software triggered interrupts.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: Minor performance improvements

This patch two performance improvements:
1. Treat all SGIs (i.e. irq < 16) as edge-triggered and
don't touch pending flag for edge-triggered interrupts
in __vgic_sync_vcpu_hwstate()
2. No need to test VGIC_TEST_ENABLED() along with
VGIC_TEST_PENDING() because an irq can only be pending
if it is enabled.

Signed-off-by: Anup Patel <anup@brainfault.org>
Merge remote-tracking branch 'upstream/master' into imx6
[ARM] vgic: Map CPU interface registers for upcoming irq routing

For routing physical interrupts to guest, we would require to exploit
the EOImode to de-prioritize physical interrupts and de-activate
physical interrupts from guest using HW bit of GICH_LRx registers.

To do the above, we would require to access GICC_EOI and GICC_DIR
register from VGIC driver hence this patch is a preparatory patch
for upcoming irq routing in VGIC.

Signed-off-by: Anup Patel <anup@brainfault.org>
Merge remote-tracking branch 'upstream/master' into imx6
[DRIVERS] fix return code in timer

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[CORE] Mandate emulator for both real and virtual device regions

Generally, we use manifest_type=virtual and
device_type!=(ram|alloced_ram|rom|alloced_rom) for
specifying emulated/virtual device.

We would be using manifest_type=real and
device_type!=(ram|alloced_ram|rom|alloced_rom) for
specifying real/pass-through device.

In addition to above, a pass-through/real device would
also require configuring IOMMU/SMMU before the device
is accessed by Guest. Upon Guest reset we might also
require to cleanup/reset device state because Guest OSes
typically don't cleanup device state on reset.

To tackle, the above we mandate emulator for both
real and virtual devices. This means for having
pass-through access to a device we will require
a emulator for it which will handle setup and
cleanup or pass-through device.

This patch updates vmm_guest_aspace and vmm_devemu
to achieve the above.

Also, this patch will break guest creation for guest
requiring VGIC hence subsequent patches fixes VGIC
emulator for allowing pass-through access to VGIC
virtual CPU interface.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] vgic: Register separate emulators for dist and cpu interface

Now we need to provide emulator for pass-through access to VGIC
virtual CPU interface hence this patch updates VGIC code to provide
two separate emulators for Guest GIC dist and Guest GIC cpu interfaces.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] No need to specify host physical address for VGIC CPU interface

Updated VGIC emulator registers separate emulator for VGIC CPU interface
which automatically updates the host physical address in Guest VGIC CPU
region hence we don't need to explicity specify it via device tree.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Add mechanism to help irqchip override/update irq handler

Some irqchips (e.g. VGIC for irq routing) may require to override or
update the current irq handler set for given host irq number.

This patch extends the host irq APIs to allow get/set of host irq
handler and host irq handler data.

Signed-off-by: Anup Patel <anup@brainfault.org>
[TESTS] Fix basic firmware Makefile.inc for native compilation

For native compiling basic firmware, the CROSS_COMPILE environment
variable will not be set hence we should not assume any cross-compile
prefix in basic firmware Makefile.inc when CROSS_COMPILE is not defined.

This patch patch fixes basic firmware Makefile.inc as-per above.

Reported-by: Puja Gupta <pmgupta.akl@gmail.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Merge remote-tracking branch 'upstream/master' into imx6