Some of the logic is jumbled up, count needs to be separated and not calculated in next-state logic, outputs show up on testbench, column is always unknown
Re-did the way count is handled gave it, its own process and made count_next reset on state transitions, also I made sure all signals are only assigned in one spot
Made the v-sync gen and testbench... pretty much the exact same thing as hsync with different timing on the states
added vga atyls_lab_video and pixel gens need to write testbenches to test as the bit file doesnt work
vsync and hsync states were all of by one clock cycle fixed that and changed next state for vsync to change off of h_completed also changed clk in atlys lab video to pixel_clk
changed clk on vga clock to pixel clk
changed all of the timing to unsigned instead of binary and backporch to one less clock cycle
changed the testbench to include my hsyncgen so it could change correctly off of vcompleted
changed pixel gen to test a simple all red case and changed vga sync back to its original
changed pixel gen and atlys to include switches also added the contraints file im so happy to be donegit statusgit statusgit statusgit status :)
Merge branch 'master' of https://github.com/cbusho/Lab1_Busho