CHROMIUM: usb: ehci-s5p: Conditionally reset HSIC phy for different boards

The HSIC phy is being reset on-the-fly unconditionally for all the
boards using ehci-s5p controller. This workaround however, should be
board dependent, so that only the boards which require, enable it.
So adding a board specific DT property for the same.
Moreover we have seen the HSIC phy reset mechanism behavior different
on different boards.
On snow things are pretty much fine, but with peach-pit and peach-pi,
a reset on HSIC phy makes the port to misbehave and thereby stopping
the 3503 hub to get detected.
Also removing the config USB_EHCI_S5P_HSIC_RESET, since we won't
require it if we have a board specific DT property.

BUG=chrome-os-partner:25212, chrome-os-partner:18932, chrome-os-partner:21952
TEST=Test on snow, peach-pit, and peach-pi; and other exynos5 based
	systems, and confirm that the HSIC hub (0424:3503) gets detected
	on them. See below result of lsusb on snow.
	localhost ~ # lsusb
	Bus 003 Device 002: ID 0424:3503 Standard Microsystems Corp.
	Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
	Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
	Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
	Bus 004 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
	Bus 003 Device 003: ID 2232:1037

Change-Id: I3b2e5e3644e02461a01e78ad2f1a8d50eafc766c
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/188999
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
CHROMIUM: config: Disable experimental HSIC phy reset.

Disable CONFIG_USB_EHCI_S5P_HSIC_RESET since we don't need it anymore
after we have a DT property to indicate resetting the PHY.

BUG=chrome-os-partner:, chrome-os-partner:18932, chrome-os-partner:21952
TEST=Test on snow, peach-pit, and peach-pi; and other exynos5 based
	systems, and confirm that the HSIC hub (0424:3503) gets detected
	on them. See below result of lsusb on snow.
	localhost ~ # lsusb
	Bus 003 Device 002: ID 0424:3503 Standard Microsystems Corp.
	Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
	Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
	Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
	Bus 004 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
	Bus 003 Device 003: ID 2232:1037

Change-Id: Ieea6d14e2de946dde82b396491f7def37053adf9
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/189040
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
HACK: exynos5420: devfreq: Set wcore frequency to 333 Mhz for all levels

On pit, video decode latency is high when wcore freq is lower.
Since voltage for all levels are the same it is safe to set
wcore frequency to 333 for all the 4 levels.

This can be reverted once a proper fix to lock devfreq lands.

BUG=chrome-os-partner:27529
TEST=Run vdau and measure decode time for 1080p vp8 stream

Change-Id: I99efe0a87f58d0700d938778bbb303e38c3a0820
Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/193003
Reviewed-by: Arun Mankuzhi <arun@chromium.org>
Tested-by: Arun Mankuzhi <arun@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Arun Mankuzhi <arun@chromium.org>
usb-phy: samsung-usb3: Add CR_PORT tuning for RxDetect_Measurement_Time

Tune proper Wait time for RxDetect measurement for desired reference
output clock frequency.
This will fix issues with few non-working USB 3.0 devices, which
are not detected and don't even generate an interrupt on the bus
without this change, e.g. Samsung SUM-TSB16S 3.0 USB drive.

BUG=chrome-os-partner:27400
TEST=Build and boot the kernel on peach-pit/pi and test with bad
     device like, Samsung SUM-TSB16S 3.0 USB drive; and see the
     device getting detected.

Change-Id: I71c50f2f0497515621d1773a1b58e6c877385481
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/191834
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: YeongGu Cho <ykn.cho@samsung.com>
t6xx:chromebook: Remove set_rate for divider clock

For Exynos5250, with GPLL rate being same as dvfs rate,
we can remove setting rate for divider clock.

For Exynos542x, clk_set_rate(platform->sclk_g3d) was returning without
changing any value as sclk_g3d is a mux clock and CLK_SET_RATE_PARENT
flag is not set.

BUG=chrome-os-partner:27635
TEST=On Both Daisy and Pi
Changed dvfs rate by stepping up and down and verified the final
and intermediate values of platform->sclk_g3d.

Change-Id: I57b066ad8c026e9fbd0099c38bb2572dd411e362
Signed-off-by: Akshu Agrawal <akshu.a@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/193012
Reviewed-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Akshu Agrawal <akshu@chromium.org>
Tested-by: Akshu Agrawal <akshu@chromium.org>
CHROMIUM: DT: Spring: Enable hsic-phy reset support

Enabling support to reset hsic phy on Spring board.

BUG=chrome-os-partner:25212, chrome-os-partner:18932, chrome-os-partner:21952
TEST=Test on Spring machine, and confirm that the HSIC hub (0424:3503)
	gets detected and see below result of lsusb.
	localhost ~ # lsusb
	Bus 003 Device 002: ID 0424:3503 Standard Microsystems Corp.
	Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
	Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
	Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
	Bus 004 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
	Bus 003 Device 003: ID 2232:1037

Change-Id: I6790f5debad2d3b1e3391f47eb93a802ecb75008
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/189041
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
CHROMIUM: ALSA: hda/realtek - Replace alc_eapd_shutup from alc283_shutup

It doesn't need to have 200ms delay.
It will save suspend time.

BUG=none
TEST=none

Change-Id: Ibd81d8a97881a3d443a1ba5d5b4a4d80800a82eb
Signed-off-by: Kailang Yang <kailang@realtek.com>
Reviewed-on: https://chromium-review.googlesource.com/178472
Reviewed-by: Chih-Chung Chang <chihchung@chromium.org>
Tested-by: Chih-Chung Chang <chihchung@chromium.org>
atmel_540s, Touch Major should get from area.

We get touch mojor from peak. But it is incorrect.
Touch major should be calculated by area.
With patch, we can get correct touch major value on pi.

BUG=chrome-os-partner:27698
TEST=Run evtest, mtplot and gesture on pi.
Check if touch_major is large with palm or not.

Change-Id: I2fa848a91919039120053c72623ee5b8f2e68ffc
Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/193578
Reviewed-by: Inno Park <ih.yoo.park@samsung.com>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Charles Mooney <charliemooney@chromium.org>
Tested-by: Charles Mooney <charliemooney@chromium.org>
Revert "CHROMIUM: ARM: mm: fix section mappings after boot"

This reverts commit 526f1cb9106d9399dc0aa12f1d642f42f9c7ae0e.

BUG=chromium:356988
TEST=spring build/boot

Change-Id: I528559f5c6f8850bfb97c47b69dd00a6130626ec
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192568
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Revert "CHROMIUM: ARM: mm: split kernel text from init"

This reverts commit e421a6b3c952625d9c098e8076a626811b842c3b.

BUG=chromium:356988
TEST=spring build/boot

Change-Id: Icdb94f4f796864c79c0f8b203b551651aa047ccb
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192569
Reviewed-by: Sameer Nanda <snanda@chromium.org>
CHROMIUM: arm: ftrace: work with CONFIG_DEBUG_SET_MODULE_RONX

Make ftrace work with CONFIG_DEBUG_SET_MODULE_RONX by making module text
writable around the place where ftrace does its work, like it is done on
x86 in the patch which introduced CONFIG_DEBUG_SET_MODULE_RONX,
84e1c6bb38eb ("x86: Add RO/NX protection for loadable kernel modules").

Tested-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: Rabin Vincent <rabin@rab.in>

BUG=chromium:356988
TEST=ftrace on daisy_spring works again

Change-Id: Id6b77c01413b469150aa40d8ab90952819be943b
(pending upstream http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8022/1)
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193481
Reviewed-by: Sameer Nanda <snanda@chromium.org>
CHROMIUM: ARM: mm: allow non-text sections to be non-executable

Adds CONFIG_ARM_KERNMEM_PERMS to separate the kernel memory regions
into section-sized areas that can have different permisions. Performs
the NX permission changes during free_initmem, so that init memory can
be reclaimed.

This uses section size instead of PMD size to reduce memory lost to
padding on non-LPAE systems.

Based on work by Brad Spengler, Larry Bassel, and Laura Abbott.

Signed-off-by: Kees Cook <keescook@chromium.org>

BUG=chromium:356988
TEST=ftrace on daisy_spring works again

Change-Id: I90ca2b91f6174cb4d4e49c375ea49970c9aeb458
(discussing w/ upstream https://lkml.org/lkml/2014/4/3/424)
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193482
Reviewed-by: Sameer Nanda <snanda@chromium.org>
CHROMIUM: ARM: mm: allow text and rodata sections to be read-only

This introduces CONFIG_DEBUG_RODATA, making kernel text and rodata
read-only. Additionally, this splits rodata from text so that rodata can
also be NX, which may lead to wasted memory when aligning to SECTION_SIZE.

The read-only areas are made writable during ftrace updates. Additional
work is needed for kprobes and kexec, so the feature is temporarily
marked as unavailable in Kconfig when those options are selected.

Signed-off-by: Kees Cook <keescook@chromium.org>

BUG=chromium:356988
TEST=ftrace on daisy_spring works

Change-Id: Ic807c347c8807ae548fe3b579b97e2f8eb449c06
(discussing w/ upstream https://lkml.org/lkml/2014/4/3/418)
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193483
Reviewed-by: Sameer Nanda <snanda@chromium.org>
CHROMIUM: config: enable ARM upstream kernel memory restrictions

This enables the proposed-to-upstream kernel memory restrictions configs:
    CONFIG_ARM_STRICT_KERNMEM
    CONFIG_DEBUG_RODATA

BUG=chromium:356988
TEST=spring build/boot

Change-Id: Ie5b6f98472441dafd16987e4d6b529ad3b93e486
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192592
Reviewed-by: Sameer Nanda <snanda@chromium.org>
UPSTREAM: Bluetooth: btmrvl: separate write-to-clear function from interrupt handler

This patch improves readability and makes future changes easier.

Signed-off-by: Bing Zhao <bzhao@marvell.com>

BUG=chrome-os-partner:26511
TEST=hciconfig up and hcitool scan work fine

Change-Id: I197273bb4356cc904911457a655b0669d4427135
Reviewed-on: https://chromium-review.googlesource.com/191933
Reviewed-by: hyuckjoo lee <hyuckjoolee345@gmail.com>
Tested-by: hyuckjoo lee <hyuckjoolee345@gmail.com>
Reviewed-by: Bing Zhao <bzhao@marvell.com>
Tested-by: Bing Zhao <bzhao@marvell.com>
Reviewed-by: Scott James Remnant <keybuk@chromium.org>
Commit-Queue: Bing Zhao <bzhao@marvell.com>
UPSTREAM: Bluetooth: btmrvl: implement read-to-clear for SD8897 interrupts

For SD8897, CMD52 write_to_clear may have missing interrupts
under certain corner case condition. Use CMD53 read-to-clear
to fix the problem.

Signed-off-by: Bing Zhao <bzhao@marvell.com>

BUG=chrome-os-partner:26511
TEST=hciconfig/hcitool works, a2dp works fine for 12+ hours
on peach_pit.

Change-Id: Id525fd8de181bdf96def10498960694a13e209f4
Reviewed-on: https://chromium-review.googlesource.com/191934
Reviewed-by: hyuckjoo lee <hyuckjoolee345@gmail.com>
Tested-by: hyuckjoo lee <hyuckjoolee345@gmail.com>
Reviewed-by: Bing Zhao <bzhao@marvell.com>
Tested-by: Bing Zhao <bzhao@marvell.com>
Reviewed-by: Scott James Remnant <keybuk@chromium.org>
Commit-Queue: Bing Zhao <bzhao@marvell.com>
CHROMIUM: Bluetooth: btmrvl: indicate pscan scheduling instant in a debug event

A vendor specific command is sent to firmware during
initialization to enable this feature. This command is for
SD8897 only.

Signed-off-by: Bing Zhao <bzhao@marvell.com>

BUG=chrome-os-partner:26511
TEST=play video clips with A2DP continuously for 4 hours.

Change-Id: I4550696e55e154d15298c429d6c1f6d7ca0d46c6
Reviewed-on: https://chromium-review.googlesource.com/192240
Reviewed-by: hyuckjoo lee <hyuckjoolee345@gmail.com>
Tested-by: hyuckjoo lee <hyuckjoolee345@gmail.com>
Reviewed-by: Scott James Remnant <keybuk@chromium.org>
Commit-Queue: Bing Zhao <bzhao@marvell.com>
Tested-by: Bing Zhao <bzhao@marvell.com>
drm/exynos: add support for interlaced modes in pi*

This patch adds support of 1440x480i and 1440x576i
resolutions in peach_pi*.
Also in the process its identified that HDMI_TG_CMD
register needs to be properly reset before
initializing it, this is required to ensure that all
other resolutions work as intended after selecting
any interlaced mode.

BUG=chrome-os-partner:27289
TEST=On Pi* connected monitor that supports 1440x480i, 1440x576i
and verifed ui

Change-Id: I078df06234d205024fa86a42d1e2a128c97a6e10
Signed-off-by: Shirish S <s.shirish@samsung.com>
[seanpaul fixed minor bitmask bug & added WXGA/SXGA mixer names]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/191644
drm/anx7808: Handle unplug of adapter during modeset gracefully

Unplugging the HDMI adapter during a modeset could cause a failure
and power off while under lock preventing the POLLING_ERR interrupt
from being handled.  The POLLING_ERR interrupt is responsible for
resetting the cable detect oneshot and this would prevent future
hotplugs from being detected.

BUG=chromium:359850
TEST=On spring unplug HDMI adapter during modeset and then plug in after POLLING_ERR interrupt has been missed

Change-Id: Ic5fdd24c990ab8c066fcb60a1276bd0d3b7abe2a
Signed-off-by: David Riley <davidriley@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193176
drm/anx7808: Avoid downstream retraining when enabling.

Key downstream retraining off of LANE0_1_STATUS_SUCCESS instead of
VIDEO_STABLE since anx7808_enable() already blocks waiting for
LANE0_1_STATUS_SUCCESS.  Without this change, retraining could be
attempted immediately after enabling.  Also update infoframes and
audio when retraining.

BUG=chromium:348169
TEST=Tested on spring with HDMI by switching modes away from and back to
HDMI on Asus PA-248Q monitor

Change-Id: I792931ac59b6278bbf7834460e6a2a0808dc22f0
Signed-off-by: David Riley <davidriley@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193177
Reviewed-by: Sean Paul <seanpaul@chromium.org>