Recompiled on new system.

Changed the system and it needed a complete recompilation. Shouldn't have changed anything in the logic though.
Included the register control into the top level module.
Selected the default iMPACT project file.
Changed the clock for the register module.
Add single register read.
Add generic device registers for two devices.
Initialization file for the ROM was missing.
Enable multithreading for place and route.
Adding a configurable clock generator to the register control.
Added the iMPACT project file to the project configuration.
A first version of the DAQ fifo for bulk data transfer.
Instatation model for DAQ fifo.
DAQ fifo is working and can be read out via single register read.
First try to modify eth_wrapper for new register handling.
First attempt for bulk transfer mode with new registers.
Converted tabs to spaces.
Switched back to my old ethernet wrapper.

The reason is that I hope to make the transition to the new register handling easier.
Made necessary changes for new register module.
Some cleanup in eth_wrapper.
Basic bulk transfer mode.

Same functionality as with the first SREGS DMA transfer, so no multiple packages and with bulk word size fixed to 32 bit.