putGST_masked: correctly handle the case where the mask is for
FPSCR.RN or FPSCR.DRN, but does not cover the entire field.  Then it
is important to update the exposed parts but leave the not-exposed
parts unchanged.  This is a regression relative to circa 5 years ago.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2929 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Bug 330319 - vex amd64->IR: unhandled instruction bytes: 0xF 0x1 0xD5 (xend)

We are never in an transaction (xbegin immediately aborts).
So this just always generates a General Protection Fault.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2931 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt
estimate and reciprocal sqrt step, to be more consistent.  Remove
64FxWhatever versions of those ops since they are never used.  As a
side effect, observe that RSqrt32Fx4 and Rsqrte32Fx4 are the same and
hence fix the duplication, at the same time.  No functional change.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2932 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: implement:
  {zip,uzp,trn}{1,2} (vector)
  urecpe, ursqrte (vector)


git-svn-id: svn://svn.valgrind.org/vex/trunk@2933 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Comment-only change.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2934 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add support for four IROps that Memcheck generates on arm64, that
the front end doesn't generate.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2935 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips: fix typo (IRType/IRTemp)

Fix typo (IRType used instead of IRTemp).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2936 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips: remove unused macro

Remove unused instance of macro ASM_VOLATILE_CASE(rd, sel).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2937 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add support for generating ProfInc sequences on ARM64, so as to
make it possible to profile vex-generated ARM64 code.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2938 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Rename Iop_Extract{64,V128} to Iop_Slice{64,V128}, improve their
documentation, and swap the sense of the first and second args
so as to be more in keeping with the rest of the ops here, so
that the more significant arg is arg1 rather than arg2.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2939 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: route all whole-vector shift/rotate/slice operations
through Iop_SliceV128, so as to give it some testing.  Implement
Iop_SliceV128 in the back end.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2940 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add a missing return statement. Spotted by the Coverity checker.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2941 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: implement Cavium BBIT0 and BBIT1 instructions

Implement Cavium specific instructions:
- BBIT0 (Branch on bit clear)
- BBIT1 (Branch on bit set)

This should fix the hang issue reported in:
https://bugs.kde.org/show_bug.cgi?id=336139


git-svn-id: svn://svn.valgrind.org/vex/trunk@2942 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: enable support for: str bN, [reg, reg etc]
and str hN, [reg, reg etc].  Fixes #337762.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2943 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: fix jmpKind for BLTZ and BGEZ

As spotted by Maran Pakkirisamy, jump kind for BLTZ and BGEZ should be
Ijk_Boring and not Ijk_Call.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2944 8f6e269a-dfd6-0310-a8e1-e2731360e62c
iselStmt, case Ist_Dirty: remove pointless conditional.  Spotted by
Coverity and Florian Krohm.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2945 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Use const instead of a comment.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2946 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Handle fcvtpu Xd,Sn.  Fixes #335564.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2947 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Minor refactoring to avoid special handling of emulation
failures in s390_irgen_PFPO.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2948 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Change how FXSAVE and FXRSTOR are done, so as to avoid pushing the XMM
register contents themselves through the helper functions.  This
avoids the false positives reported in #291310.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2949 8f6e269a-dfd6-0310-a8e1-e2731360e62c