the DMA for both assembling and transmitting the blocks are both active at the same time and seem to work. However,
there appears to be a 1/30 duty cycle glitch where the output of the McASP seems to overshoot a lot more than necessary.
I am also worried about having both DMA processes on the same channel/transfer controller set, and should probably move
one of them from channel controller 0 to channel controller 1.