Added registered parameter to Address_Translator

Registers don't see to retime past this module. Hence the change.
WARNING: See comments. Must feed a RAM directly, else a small RAM
instantiates for translation, instead of optimizing away.
Adjusted to match new registerable Address_Translator
Pipelined write addr/data decoding and translating.

This reduces the overhead from baseline (original Octavo) from 3% to 1%!!!
Fmax: 503/522/540
No observable common critical path now.
Pipelining same for I_mem might be nice if needed.
Added address translators to I/A/B mem write addresses.

We got away without since they were aligned in memory space.
Now, the addressing will work right regardless of memory mapping.
No area impact.
Current area, with folding and cancelling branches:
1132 ALMs (one example), that's 57% to 77% larger than baseline.