arm: dts: zc706-vdf: Add HDMI capture pipeline

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] arm: dts: zynq-zc706: Boot over NFS

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] media: xiling: tpg: Raise vertical blanking

This lowers the frame rate to around 60fps with the VDF design.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] media: xilinx: tpg: Add video timing mux support

The current version of the TPG core has no video timing input interface
but requires video timings to be supplied through its AXI stream slave
interface when generating a test pattern.

The VDF design thus instantiates a video timing mux in front of the
video 2 AXI stream core. The mux is controlled through a GPIO, which
needs to be controlled by the TPG driver.

Future versions of the TPG core will have a video timing input
interface, removing the need for GPIO mux control.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[HACK] arm: dts: zc706-vdf: Add video timing mux GPIO to TPG

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
arm: dts: zc706-vdf: Add clock property to VTC

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] media: xilinx: vtc: Add interrupt support

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] media: xilinx: Add register read/write debug to TPG and VTC

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] media: xilinx: Add debugging messages

Trace VTC and TPG start/stop and print the TPG status when VTC
interrupts occur.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[DEBUG] dma: xilinx: vdma: Add debugging messages

Print all register accesses and trace several operations.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
media: xilinx: Add AXI4 stream switch driver

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>