mibuild/xilinx_vivado.py: add set property to misc constraint
Merge branch 'master' of github.com:m-labs/migen
mibuild/generic_platform.py: adding ability to use void pins (none fpga pin) for connectors

Signed-off-by: Fabien Marteau <fabien.marteau@armadeus.com>
mibuild/platforms: add APF27 and APF51 Armadeus platforms
genlib/SyncFIFO: remove flush signal (use InsertReset instead)
flow.plumbing: make argument order consistent
flow.plumbing: spelling
migen/sim/generic: use kwargs to pass parameters to icarus.Runner
migen.fhdl.structure: add Signal.like(other)

This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
mibuild.xilinx_vivado: support settingsXX.sh

* in the process refactor the version search, the architecture bit width
 detection, the settings search and all also for xilinx_ise
* use distutils.version.StrictVersion
kc705: add ddram pins
mibuild/xilinx_vivado: allow sharing Misc constraints with ISE: example: ISE: DIFF_TERM=True VIVADO: set property DIFF_TERM TRUE
kc705/ddram: use lighter pin syntax
mibuild: move programmer to mibuild and create programmer directly in platforms
genlib/fifo: use synchronous memory read instead of additional register

The latter causes problems with InsertReset
mibuild/generic_platform: add recursive parameter to add_source_dir
mibuild/programmer: fix XC3SProg init
platforms/kc705: use Vivado by default
platforms/kc705: use XC3SProg
platforms/kc705: add automatic clk200 constraint