Documentation: devicetree: Fix Xilinx VDMA specification

The specification requires xlnx,data-width, but example and driver use
xlnx,datawidth. Change the specification to match the implementation.

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: Enable PL clocks for Parallella

The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 by default for the Programmable Logic.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev using /dev/mem.

Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
pinctrl: pinconf-generic: Add flag to print arguments

When dumping pinconf information in debugfs, config arguments are only
printed when a unit is present and the argument is != 0. For parameters
like the slew rate, this does not work. The slew rate uses a driver
specific format for the argument, i.e. 0 can be a valid argument and a
unit is not provided for it.
For that reason, add a flag to enable printing the argument instead of
inferring it from the presence of a unit and the value of the argument.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
pinctrl: pinconf-generic: Declare dt_params/conf_items const

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
pinctrl: pinconf-generic: Infer map type from DT property

With the new 'groups' property, the DT parser can infer the map type
from the fact whether 'pins' or 'groups' is used to specify the pin
group to work on.
To maintain backwards compatibitliy with current usage of the DT
binding, this is only done when an invalid map type is passed to the
parsing function.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
pinctrl: pinconf-generic: Allow driver to specify DT params

Additionally to the generic DT parameters, allow drivers to provide
driver-specific DT parameters to be used with the generic parser
infrastructure.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
pinctrl: zynq: Document DT binding

Add documentation for the devicetree binding for the Zynq pincontroller.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
pinctrl: Add driver for Zynq

This adds a pin-control driver for Zynq.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
ARM: zynq: Enable pinctrl

Select pinctrl and the Zynq pinctrl driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
ARM: zynq: DT: Add pinctrl information

Add pinctrl descriptions to the zc702 and zc706 device trees.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
ARM: dts: zynq: Add pinctrl to Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add VDMA to Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add SPDIF for Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add AXI clkgen for Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
usb: chipidea: zynq: Add device tree binding information

Document device tree binding information as required by
the ZYNQ USB controller.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
usb: chipidea: Add support for zynq usb host and device controller

Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
necessary glue to allow the chipidea driver to work on zynq soc.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
TEST_ONLY: ARM: dts: zynq: Add USB to Parallella

Awaiting generic Chipidea driver and bindings, this wires up the
proposed v2 of a Zynq-specific driver.

Signed-off-by: Andreas Färber <afaerber@suse.de>
USB update
ARM: dts: zynq: Add QSPI for Parallella [HACK]

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: parallella: Try adding flash

Signed-off-by: Andreas Färber <afaerber@suse.de>