ARM: 7587/1: implement optimized percpu variable access

Use the previously unused TPIDRPRW register to store percpu offsets.
TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.

This replaces 2 loads with a mrc instruction for each percpu variable
access. With hackbench, the performance improvement is 1.4% on Cortex-A9
(highbank). Taking an average of 30 runs of "hackbench -l 1000" yields:

Before: 6.2191
After: 6.1348

Will Deacon reported similar delta on v6 with 11MPCore.

The asm "memory clobber" are needed here to ensure the percpu offset
gets reloaded. Testing by Will found that this would not happen in
__schedule() which is a bit of a special case as preemption is disabled
but the execution can move cores.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>

Conflicts:
	arch/arm/kernel/smp.c
Something else
add BadAss CPU gov

Conflicts:
	drivers/cpufreq/Kconfig
	drivers/cpufreq/Makefile

Conflicts:
	drivers/cpufreq/Kconfig
	drivers/cpufreq/Makefile
boost volume
Defconfig
msm:pm: Fix for race condition of starting cpu1 when cpu0 in PC.

There is a window where core sends ipi to secondary core and
wait for it to come online for 1 second. This would allow
core0 to go power collapse in a rare condition where core1
started booting and doesn't become online yet.

Fix this by not allowing power collapse on core0
if hot plug operation is in progress.

CRs-fixed: 545714.
Change-Id: I1ca503a2f09cd9a65c2fdcd41eb54466a1e486c5
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/pm-8x60.c
Fix
cpufreq: intellidemand: added miss cpufreq register declarations
Parking this WIP to catch up thermald and mpdecision removal first.

Conflicts:
	arch/arm/Makefile
	arch/arm/mach-msm/acpuclock-8064.c
BADASS
Clean