Squashed commit of the following:

commit f73d6cf0fcae5f401fc2817ab736af996113ca09
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Thu Apr 24 15:02:21 2014 +0800

    remove comments

commit 75416c2cf6c1ebb7aabf9e8c52d8c7163a8009b7
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Thu Apr 24 14:52:09 2014 +0800

    for test

commit 7dfb65ce514edcff892bfb3919921cadcce1d055
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Thu Apr 24 14:12:31 2014 +0800

    for test

commit eff771645e8c349dc4e454ab1751530b3cef18ed
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Thu Apr 24 10:51:34 2014 +0800

    for test

commit 9c42b9a7a04068e70be94529941f549b58e63780
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Wed Apr 23 17:46:59 2014 +0800

    update cpu_flag

commit cce3fccc0a4249b82ab2e0e92fe53579ef942799
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Wed Apr 23 17:26:56 2014 +0800

    for test

commit 3d292995b3c4437a2674a687cc4e8da1b5fb83f5
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Wed Apr 23 16:45:57 2014 +0800

    remove space

commit c608c2ba7cf010f1dcf8c0344f68536c48e181cb
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Wed Apr 23 16:42:43 2014 +0800

    remove tabs

commit 3b769342a06e25ad23a2c86f23a94d0d7ca1a4c8
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Wed Apr 23 16:33:55 2014 +0800

    refine UT case

commit 89b869f0c8f8c9bbd61e9de32caa77877aeae064
Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
Date:   Tue Apr 22 13:40:50 2014 +0800

    Squashed commit of the following:

    commit abe55494134ef8342ffe9566df4e1b3265fe21b6
    Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
    Date:   Tue Apr 22 10:50:07 2014 +0800

        set MV range

    commit 8c7f70c351e50d945c29118bed8b3781c22b7dbc
    Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
    Date:   Mon Apr 21 16:53:10 2014 +0800

        refinement

    commit bf35f19a7dc88743aacf8e89e681e0ef3302d40a
    Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
    Date:   Fri Apr 18 17:24:31 2014 +0800

        correct tabs

    commit 130b7f895d7020bfc571d910966891da93150242
    Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
    Date:   Fri Apr 18 17:17:06 2014 +0800

        correct format

    commit 0429703b0844363559dd2b3d44e45034232a9d8f
    Author: lyao2 <lyao2@LYAO2-WS01.cisco.com>
    Date:   Fri Apr 18 15:12:44 2014 +0800

        add scroll UT
fix bug of new seq check
Merge pull request #745 from lyao2/scrollingUT

add scroll detection UT
Remove dos newlines in the android java code
use new seq instead of I slice
Merge pull request #748 from huili2/newSeq_bugfix

fix bug of new seq check
Check for WELS_CPU_NEON before calling DeblockingBSCalcEnc_neon

Checking HAVE_NEON is not enough; e.g. android devices with
armeabi-v7a are not required to have NEON, so every use of such
functions should be check WELS_CPU_NEON in the cpu features
as well.
Merge pull request #749 from mstorsjo/dos-newlines

Remove dos newlines in the android java code
Merge pull request #750 from mstorsjo/deblocking-neon-cpu-features

Check for WELS_CPU_NEON before calling DeblockingBSCalcEnc_neon
refine pNzc set access
Merge pull request #751 from huili2/NewSeq_replace_I

use new seq instead of I slice
Do full register loads instead of single-lane loads in DeblockLumaEq4H_neon

Instead of loading the registers one lane at a time, load full
registers and then transpose them.

This is faster, reducing the runtime for the function from about
506 cycles to 434 cycles (tested on a Cortex A8).

This also avoids an issue which seems like a cpu bug, present
on Sony Xperia T (cpu implementer 0x51 architecture 7 variant 0x1
part 0x04d). On such a device, it seemed like the "vswp q9, q10"
could start executing before the previous
vld4.u8 {d20[x],d21[x],d22[x],d23[x]}, [r3], r1
had finished and written back their result. Changing the
"vswp q9, q10" into "vswp q10, q9", or into separate
"vswp d18, d20; vswp d19, d21" (or the other way around) seemed to
avoid the issue. This happened occasionally (a couple times per
100000 invocations or so).
Merge pull request #755 from licaiguo/refine-pNzc

refine pNzc set access
Merge pull request #759 from mstorsjo/deblock-neon-transpose

Do full register loads instead of single-lane loads in DeblockLumaEq4H_neon