Fix the context switch code so the correct VA is used for the 2nd page set.

This change fixes the context switch code uses the correct virtual address
for the second page set (or second wired TLB entry) for the kernel thread
stack.  The second set of pages are below (and not above) the first set.
This change also turns on 16K kernel thread stack, by default, for
mips n64 builds.
Merge branch 'master' of https://github.com/CTSRD-CHERI/cheribsd