Re-enabled callbacks
Check "evaluate" box for parameter ttl

Otherwise it doesn't get properly evaluated when writing peripherals
file
Fix bug in constraint gen, improve core_info.tab

1) Fix bug where constraints that don't start at port index 0
aren't evaluated properly.

2) Use nicer formatting when generating strings for core_info.tab
to make things line up nicer
Add a few print statements
Add unique_name attribute to yellow blocks.

This is the one used for wishbone names. It is the same hierarchical
block name as used in the old toolflow
Add support for multiple WB interfaces.

A single module can now have multiple wishbone interfaces with ports
distinguished by a suffix.

Also changed some of the immutability stuff so that whitespace in names
doesn't mess up ability to recognise two ports/signals as the same.
Changed immutability so that attributes equal to None can be
overwritten. This allows 'signal' to be added as a constructor argument
to ports, allowing a signal to be specified positionally, and saving
irritating signal=... arguments for simple port cases.
Working 10GbE! (tested with tut2)

Created two directories of hdl files for code that has changed between
virtex 6 and kintex 7.

yellow block constructor now attempts to call a factory method when
initialising, allowing different subclasses of yellow blocks to be used
for different platforms. This is done for the ten_gbe_v2 yellow block
class.

10gbe tested with roach2 tutorial 2 (I was manually setting the arp
table, need to check tap_start works properly).

note: I changed hdl_sources/kat_ten_gb_eth/wb_attach.v because the arp
table wasn't being written correctly. TODO: work out why the old code
didn't work...