[TASK] Cleanup AXI slave wrapper

- Do modification avoiding combination logic from mux as per Xilinx Design
  Guidelines
- Update comments and documentation part

Change-Id: I028b2b592650bcb5ba32a40d81849ebed8df33e2
[FEATURE] Enable AXI master supporting higher clock frequency

- Add registers at input from host interface avoiding glitches on AXI master
- Add FSM making sure transfer completion on master and slave side
- Update toplevel and testbench
- Add descriptions and code cleanup

Change-Id: I3e836e2c8dab0600f0d15fe065832ccb10d0376c
[TASK] Cleanup and update xps support for host interface

- Update tcl script for version and revision details
- Add license headers and cleanup files

Change-Id: If70a8304d820189652092326e7c37a02fb88fa68