[pcie_hdl] Switch to using OHWR general-cores whenever possible.
This will allow greater code reuse and greater flexibility over using
COREGEN generated FIFO & BRAM modules.
Changes to DDRs_Control module are still needed, but will happen a bit
later as this module needs some refactoring.
[pcie_hdl] Cleanup some dead code & update .xise project files.
[pcie_hdl]Switch to level triggering to fix deadlock
in TLP preprocessing FSM.
[pcie_hdl]: Remove leftover code.
pcie_hdl: Clear Wishbone read FIFO after TX reset.
If Wishbone transaction timed out, tx_mem_reader will signal this and
start sending FFs until reset command is issued. However, there can be
scenario when data comes from Wishbone bus after the timeout and is put
in the FIFO. Resetting tx_mem_reader module doesn't clear read FIFO
which causes that during subsequent reads data from old, unsuccesfull
reads is returned instead of recent data.
Also, explicitly define default value for wb_timeout signal.
Merge branch 'master' into dsp-devel
hdl/ip_cores/general-cores: update submodule reference