For level triggered interrupts clear the PIC IRR bit when the interrupt pin
is deasserted. Prior to this change each assertion on a level triggered irq
pin resulted in two interrupts being delivered to the CPU.

Differential Revision:	https://reviews.freebsd.org/D1310
Reviewed by:	tychon
MFC after:	1 week


git-svn-id: svn+ssh://svn.freebsd.org/base/head@275817 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f