Fix for GitHub issue 25 - compiler crash when function declared outside module.

This is an error in traditional Verilog and a unsupported feature in
SystemVerilog. Fail gracefully with a suitable error/sorry message.
Do the same for task declarations.
Merge branch 'master' of git://github.com/steveicarus/iverilog
Fix for GitHub issue 26 - compiler crash when module port has no internal net.

The compiler correctly reports an error when a module port has no
associated internal net/reg, but could crash when the module was
instantiated.