ARM: dma-mapping: don't allow DMA mappings to be marked executable

DMA mapping permissions were being derived from pgprot_kernel directly
without using PAGE_KERNEL.  This causes them to be marked with executable
permission, which is not what we want.  Fix this.

Change-Id: Ib40f59f3c569f82409943cf8f9a86a9869d922cc
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-commit: 0ea1ec713f04bdfac343c9702b21cd3a7c711826
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[lauraa@codeaurora.org: dropped functions not in older builds]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
net: ipc_router: Defer workqueue initialization

IPC Router workqueue is initialized before some of the core IPC router
data structures are initialized leading to uninitialized data structure
access.
Initialize the workqueue after initializing the core data structures.

CRs-Fixed: 611234
Change-Id: Ia6fbd2f517afcde30b2c924507fbb9f28ccc01e3
Signed-off-by: Zaheerulla Meer <zmeer@codeaurora.org>
Merge "net: ipc_router: Defer workqueue initialization"
USB: ci13xxx_udc: Add timeout of 100ms for endpoint flush loop

Currently completion of endpoint flush operation is checked after
setting that endpoint bit with ENDPTFLUSH register and polling the
same to get it clear. It has been observed that sometime this flush
operation takes huge amount of time which results into watchdog
timeout issue due to this busy loop without any time-out. Hence add
time-out of 100ms for endpoint flush operation completion and also
add 100us delay before checking ENDPTFLUSH register for endpoint bit
clear or not.

Also print important usb status register and flushed endpoint dtds
at the time of issue.

CRs-Fixed: 654328
Change-Id: I7ae57cc436077f8a03051b92750bdca9a571da2b
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
USB: ci13xxx_udc: Don't flush inactive endpoints

The endpoint must be flushed prior to retiring pending requests.
This is done during disabling an endpoint.  Don't flush an endpoint
if there are no pending requests.  According databook flushing
endpoint may take large amount of time.  This optimization will
make USB disconnect/reset processing a little bit faster.

CRs-Fixed: 654328
Change-Id: I035b624dbac4529bbe33a67f9e7e1916d4772d6f
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
USB: ci13xxx_udc: Skip flushing endpoints upon failure

Flushing an endpoint involve polling ENDPTFLUSH and ENDPTSTAT
registers.  The worst case timeout is 100 msec for each endpoint.
The reason for failure is unknown.  When flushing an endpoint
fails, successive flushing of remaining endpoints are also failing.
Hence skip flushing remaining endpoints.  Reset this condition
upon USB bus reset.

CRs-Fixed: 654328
Change-Id: I9feeeb434dc180f1df859275ef1364c7dd829d78
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
USB: ci13xxx_udc: Flush ep0 even when queue is empty

The endpoint must be flushed before retiring pending requests. The
current code skips flushing an endpoint if there are no pending
requests.  Flushing ep0 for every setup packet is some how resolving
the race between transfer completion interrupt and transfer descriptors
updates to the system memory in the controller.  Always allow flushing
ep0 endpoint.  This patch resolves USB disconnect issue during RNDIS
high bandwidth tests.

CRs-Fixed: 654328
Change-Id: Ia89b2dc8ff831641dafb91196e3af5271ac66cfd
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Merge "ARM: dma-mapping: don't allow DMA mappings to be marked executable"
Merge "USB: ci13xxx_udc: Add timeout of 100ms for endpoint flush loop"
Merge "USB: ci13xxx_udc: Don't flush inactive endpoints"
Merge "USB: ci13xxx_udc: Skip flushing endpoints upon failure"
Merge "USB: ci13xxx_udc: Flush ep0 even when queue is empty"
soc: qcom: smd: Validate read and write addresses

The address from which data has to be read and the address to which the
SMD data has to be written is calculated based on the head and tail
indices for that SMD FIFO. If the indices are corrupted, then the
calculated pointer may be outside of the FIFO and may even be outside of
the range of SMEM.

Validate the read and write addresses to be with in the limits of
receive and send FIFO limits respectively.

CRs-Fixed: 550527
Change-Id: Ie5578f6aee73ea2b1435fea7c2a0a6dda14bff82
Signed-off-by: Zaheerulla Meer <zmeer@codeaurora.org>
[PATCH] Staging: android: binder: More offset validation.

Make sure offsets don't point to overlapping flat_binder_object
structs.

Change-Id: I425ab0c46fbe2b00ed679c5becf9e8140395eb40
Signed-off-by: Arve HjÃ¸nnevÃ¥g <arve@android.com>
Merge "soc: qcom: smd: Validate read and write addresses"
Merge "[PATCH] Staging: android: binder: More offset validation."
msm: kgsl: Mark the IOMMU setstate memory as read only

Mark the IOMMU setstate memory as read only in the pagetable.

Change-Id: Ic0dedbadb19e499c749cd744c3e89be3bcb4c2a2
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Setup a3xx protection in its start function

Setup the protection registers for a3xx towards the end of its
start function instead of doing it in generic ringbuffer start

Change-Id: I66df496afa5d1fdf7dea790306f5358c2098674d
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
msm: kgsl: Protect CP_STATE_DEBUG_INDEX

Put CP_STATE_DEBUG_INDEX and CP_STATE_DEBUG_DATA under protection
to keep it from being written from an IB1. Doing so however opens
up a subtle "feature" in the microcode: memory read opcodes turn off
protected mode in the microcode to do the read and then turns it
back on regardless of the initial state. This is a problem if the
memory read happens while protected mode is turned off and then we
try to access a protected register which then complains and goes boom.

To account for this irregularity explicitly turn back off protected
mode in all the places where we know this will be a problem.

Change-Id: Ic0dedbad1397ca9b80132241ac006560a615e042
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Enable protected mode for A3XX

Enable protected register mode for A3XX with these commits from
msm-3.10:

msm: kgsl: Enable protected register mode for A3XX
msm: kgsl: Print the register that causes a protected mode error
msm: kgsl: Unprotect the VBIF performance counters

Change-Id: Ic0dedbad950ffbd063fd861d9440bb5dce8d5fb1
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>