Added delayLine to determine when to use the non delayed or delay signal

5 1 1 8 0x0008 1128 0x009d 0x00aa 0x00a8 0x00a8 0x0007 0x2003 0x2103 0b1 0b1
5 1 0 332 0x014c 1128 0x009d 0x00aa 0x00a8 0x00a8 0x0007 0x2003 0x2103 0x00a8 0b1 0b1
5 0 0 89 0x0059 1128 0x009d 0x00aa 0x00a8 0x00a8 0x0007 0x2003 0x2103 0b1 0b1
5 0 1 251 0x00fb 1128 0x009d 0x00aa 0x00a8 0x00a8 0x0007 0x2003 0x2103 0b1 0b1

Computing the loc.lift using the left_r sam_r and right_r returned from FPGA
8 	0x0008
332 	0x014c
89	0x0059
251	0x00fb

Modified the delay_tests/std_sig.vhd to match fast_clk_jpeg/top_level_mod.vhd
added delayLine to delay_tests/std_sig.vhd