bsps: Fix empty interrupt handler entry

The vector number of spurious interrupts was wrong after the interrupt
handler removal on SMP configurations.
bsps: Delete LEON3_FATAL_CPU_COUNTER_INIT
bsp/leon3: Use ambapp_freq_get() for CPU counter
sptests/spcache01: Detect write-through cache
rtems: Cache manager documentation

Move useful functions to the top of the file.
rtems: Use size_t for cache line size

A cache line cannot have a negative size.
rtems: Add cache size functions

Add rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size().
bsp/leon3: Add and use cache register functions
bsp/leon3: Add new cache manager implementation

The previous implementation used an instruction cache line size of 0,
this is a bogus value.  Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64.  A greater value should
cause no harm.

Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().

This is a preperation step to support the L2 cache.
bsp/leon3: Add L2C registers
bsp/leon3: Add L2 cache support
tmtests/tmcontext01: New test