[gcc]
2014-11-14  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (easy_fp_constant): Delete redunant
	tests for 0.0.

	* config/rs6000/vector.md (VEC_R): Move secondary reload support
	insns to rs6000.md from vector.md.
	(reload_<VEC_R:mode>_<P:mptrsize>_store): Likewise.
	(reload_<VEC_R:mode>_<P:mptrsize>_load): Likewise.
	(vec_reload_and_plus_<mptrsize>): Likewise.

	* config/rs6000/rs6000.md (Fa): New mode attribute to give
	constraint for the Altivec registers for a type.
	(RELOAD): New mode iterator for all of the types that have
	secondary reload address support to load up a base register.
	(extendsfdf2_fpr): Use correct constraint.
	(copysign<mode>3_fcpsgn): For SFmode, use correct xscpsgndp
	instruction.
	(floatsi<mode>2_lfiwax): Add support for -mupper-regs-{sf,df}.
	Generate the non-VSX instruction if all registers were FPRs.  Do
	not use the patterns in vsx.md for scalar operations.
	(floatsi<mode>2_lfiwax_mem): Likewise.
	(floatunssi<mode>2_lfiwzx): Likewise.
	(floatunssi<mode>2_lfiwzx_mem): Likewise.
	(fix_trunc<mode>di2_fctidz): Likewise.
	(fixuns_trunc<mode>di2_fctiduz): Likewise.
	(fctiwz_<mode>): Likewise.
	(fctiwuz_<mode>): Likewise.
	(friz): Likewise.
	(floatdidf2_fpr): Likewise.
	(floatdidf2_mem): Likewise.
	(floatunsdidf2): Likewise.
	(floatunsdidf2_fcfidu): Likewise.
	(floatunsdidf2_mem): Likewise.
	(floatdisf2_fcfids): Likewise.
	(floatdisf2_mem): Likewise.
	(floatdisf2_internal1): Add explicit test for not FCFIDS to make
	it more obvious that the code is for pre-ISA 2.06 machines.
	(floatdisf2_internal2): Likewise.
	(floatunsdisf2_fcfidus): Add support for -mupper-regs-{sf,df}.
	Generate the non-VSX instruction if all registers were FPRs.  Do
	not use the patterns in vsx.md for scalar operations.
	(floatunsdisf2_mem): Likewise.
	(reload_<RELOAD:mode>_<P:mptrsize>_store): Move the reload
	handlers here from vector.md, and expand the types we generate
	reload handlers for.
	(reload_<RELOAD:mode>_<P:mptrsize>_load): Likewise.
	(vec_reload_and_plus_<mptrsize>): Likewise.

	* config/rs6000/vsx.md (vsx_float<VSi><mode>2): Only provide the
	vector forms of the instructions.  Move VSX scalar forms to
	rs6000.md, and add support for -mupper-regs-sf.
	(vsx_floatuns<VSi><mode>2): Likewise.
	(vsx_fix_trunc<mode><VSi>2): Likewise.
	(vsx_fixuns_trunc<mode><VSi>2): Likewise.
	(vsx_float_fix_<mode>2): Delete DF version, rename to
	vsx_float_fix_v2df2.
	(vsx_float_fix_v2df2): Likewise.

[gcc/testsuite]
2014-11-14  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/ppc-fpconv-1.c: Adjust for -mupper-regs-df
	changes.
	* gcc.target/powerpc/ppc-fpconv-2.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-3.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-4.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-5.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-6.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-7.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-8.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-9.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-10.c: Likewise.
	* gcc.target/powerpc/ppc-round.c: Likewise.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217590 138bc75d-0d04-0410-961f-82ee72b054a4
[AARCH64] Add scheduler for ThunderX

This adds the schedule model for ThunderX. There are a few TODOs in that
not all of the SIMD is model currently.  Also the idea of a simple
shift/extend is not modeled and all cases where there is a shift/extend
is considered as non simple and take up two cycles rather than correct
value of one cycle.  Also the 32bit divide and the 64bit divide
have different cycle counts but there is no way to model that currently.
Also multiply high takes one cycle more than the normal multiply but
there is no way to model that currently either.

Build and tested for aarch64-elf with no regressions.

ChangeLog:
* config/aarch64/aarch64-cores.def (thunderx): Change the scheduler
over to thunderx.
* config/aarch64/aarch64.md: Include thunderx.md.
(generic_sched): Set to no for thunderx.
* config/aarch64/thunderx.md: New file.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217593 138bc75d-0d04-0410-961f-82ee72b054a4