software/fpga: remove unused RXCStream
software/fpga: add timestamps to packet captures

Transmit a 3 byte timestamp with every packet.
add missing ov_types.py
software/fpga/whacker/utils: fix potential ordering issue
software/fpga/whacker: add start-of-capture/end-of-capture bits to packet header
software/host: cleanup sniffing path code
software/fpga: Register SDRAM outputs

Registering SDRAM outputs helps to improve SDRAM timing. Prequisite for
constraining SDRAM paths.
software/fpga/sdram: update comments
software/fpga: Extract SDRAM controller from FIFO

- Create a new SDRAM controller without builtin fifo logic. This SDRAM
controller implements a simple streaming master interface at the width
of the SDRAM that hides SDRAM quirks.

- Add testbench for SDRAM controller
software/fpga/sdram_mux:

- Add a roundrobin SDRAM arbiter + tests
software/fpga/sdram: Replaced SDRAM controller, added BIST

	- FPGA hardware now supports onboard BIST
	- Added support for SDRAM BIST to ovctl
		(report and sdramtest commands)
software/fpga: Initial reorganization
Update migen to most recent version
software/fpga: SDRAM Simulation Rework

	- factor out shared SDRAM test infrastructure
	- unify testcases
	- add SDRAM platform information
	- cleanup test infra
	- add make test/testall
software/fpga: Move register-map generation

Moved register-map generation from top.py to build.py.
software/fpga: Cleanup top + gpio modules
software/fpga: Cleanup clocking
software/fpga: cleanup top and sdram bist
software/fpga: Cleanup top + ULPI

	ULPI PHY interface code moved from top to submodule
software/fpga: remove unused imports