More cleanup from test code review

This is the second half of the changes I made to the test code based on
rereading the ARMv6-M ARM and the test source code.
* Update branch tests to jump to valid memory and place NOP instruction
  at the target address.
* Update comments to make the test purpose clearer to me on reread.
* Combine lowest field values with highest field values.  This makes
  sure that fields aren't flipped in the decoding phase.  For example
  having all tests of the form "op R7, R7 "-or- "op R7, #-1" wouldn't
  be good.  I also modified some tests to introduce intermediate
  register indices instead of just using R0 and R7 over and over again.
* Add POP test which hits the HardFault case when you try to branch the
  PC to an even address which isn't allowed in Thumb.
* STM tests were using raw numbers for register indices instead of the
  more descriptive R0, R1, etc macros.
* Added signed/unsigned extension tests to make sure that the upper
  bits are always overwritten.
* There are some instructions which set N and Z flags but should leave
  the C (carry) bit unmodified.  Typically the random initial state of
  the APSR bits will make sure that carry clear and set make it through
  unmodified.  I modified tests such as this to make sure that they
  explicitly validate that carry set and carry clear states are both
  maintained.