Add a NOP to thread 1-7 to initially order them as expected (0-7)

The phase of this order does not keep across I/O stalls.
This is normal, since the EF signals change asynchronously to the threads.
Translate write addresses for each memory, else writes go to an offset location.

Since memory mappings are not always aligned to 0, we must use this.
No hardware cost.
Must merge/cherry-pick this fix to pattern_matching branch.
Added correct initial values for delay registers. Fixes major hidden bug.

Previously hidden by padding NOPs at thread start.
Otherwise, the X values propagate and get written to A @ address 0, which breaks many things.
A/B/I[0] MUST hold 0 for programming and processor startup reasons.
(see Controller, which emits duplicate 0 PCs at start)
hailstone demo, now with folded branches! (2 out of 3)

Reduced cycle count by 14.2% vs. branches on NOPs.
Min/Avg/Max Fmax over 10 seeds runs: 504/527/545 MHz
Branch Folding unit with 4 entries: ~398 ALMs