Fix timer overflow code.

Teensy doesn't need to worry about overflows since all of
its timers are only 16-bit.

For PWM, the pulse width needs to be able to vary from 0..period+1
(pulse-width == period+1 corresponds to 100% PWM)

I couldn't test the 0xffffffff cases since we can't currently get a
period that big in python. With a prescaler of 0, that corresponds
to a freq of 0.039 (i.e. cycle every 25.56 seconds), and we can't
set that using freq or period.

I also tested both stmhal and teensy with floats disabled, which
required a few other code changes to compile.
Merge pull request #877 from dhylands/timer-overflow

Fix timer overflow code.