intel: Fix initial MakeCurrent for single-buffer drawables

Commit 05da4a7a5e7d5bd988cb31f94ed8e1f053d9ee39 attempts to eliminate the
call to intel_update_renderbuffer() in the case where we already have a
drawbuffer for the drawable.  Unfortunately this only checks the
back left renderbuffer, which breaks in case of single buffer drawables.

This means that the initial viewport will not be set in that case.  Instead,
we now check whether the initial viewport has not been set, in which case
we call out to intel_update_renderbuffer().

https://bugs.freedesktop.org/show_bug.cgi?id=73862

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
gallium/vl: use u_upload_mgr to upload vertices for vl_compositor

This is the recommended way for streaming vertices. Always use this if you
need to upload vertices every frame.

Reviewed-by: Christian König <christian.koenig@amd.com>
gallium/hud: just unmap the upload vertex buffer instead of recreating it
gallium/u_upload_mgr: don't expose u_upload_flush

It's unused and shouldn't be used at all in my opinion.

If some driver doesn't support the unsynchronized flag, u_upload_mgr should
avoid the synchronization by other means, e.g. by using the DONTBLOCK flag.
r600g,radeonsi: if discarding whole buffer range, discard whole resource instead

Also set the unsynchronized flag if the whole resource was discarded
to avoid doing buffer-busy checks again.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: handle R600_CONTEXT_PS_PARTIAL_FLUSH in si_emit_cache_flush

For consistency only, This is unused by radeonsi currently.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: use hardware scissors correctly

Use the WINDOW and VPORT scissors for the framebuffer and scissor test,
respectively. The other two scissors are disabled (they cover the max fb size).

We actually have 16 VPORT scissors, which will map well to ARB_viewport_array.

Also, we don't need to write SC_WINDOW_OFFSET with this commit, because it's
disabled everywhere.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
gallium: remove PIPE_CAP_SCALED_RESOLVE

If any driver doesn't support this, it can use a blit after resolving
the samples.

Reviewed-by: Brian Paul <brianp@vmware.com>
gallium/util: util_format_srgb should not return FORMAT_NONE for sRGB formats

This fixes a serious regression introduced
in 4e549ddb500cf677b6fa16d9ebdfa67cc23da097.

Cc: 9.2 10.0 <mesa-stable@lists.freedesktop.org>

Reviewed-by: Brian Paul <brianp@vmware.com>
i965: Use get_element_ud to shorten texture header access.

This is shorter, easier to read, and further from the 80 column limit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: Refactor sampler message header to duplicate less code.

Previously, the code to copy g0 to the message header existed in two
places - one for the texture offset case, and one for any other case.

By treating texture_offset as a special case of header_present, we can
remove this duplication and shorten the code.  Future patches which add
new header fields also won't have to add additional duplication.

This also clarifies a confusing construct.  The old code contained:

   } else if (inst->header_present) {
      if (brw->gen >= 7) {
         ...explicit copy from g0 to the message header...
      } else {
         /* Set up an implied move from g0 to the MRF. */
      }
   }

This looks like it might set up an implied move on Sandybridge, which
doesn't support those.  However, Sandybridge only uses a message header
for texture offsets, so it would never hit this code path.  The new code
avoids this implicit knowledge by only setting up an implied move on
Gen4-5.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: Plumb sampler index into emit_texture_gen7.

We'll need this in the next patch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: Support arbitrarily large sampler state indices on Haswell+.

The message descriptor's "Sampler Index" field is only 4 bits (on all
generations of hardware), so it can only represent indices 0 through 15.

Haswell introduced a new field in the message header - "Sampler State
Pointer".  Normally, this is copied straight from g0, but we can also
add a byte offset (as long as it's a multiple of 32).

This patch uses a "Sampler State Pointer" offset to select a group of
16 sampler states, and then uses the "Sampler Index" field to select
the state within that group.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/vec4: Don't set header_present if texel offsets are all 0.

In theory, a shader might use textureOffset() but set all the texel
offsets to zero.  In that case, we don't actually need to set up the
message header - zero is the implicit default.

By moving the texture_offset setup before the header_present setup, we
can easily only set header_present when there are non-zero texel offset
values.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/vec4: Refactor sampler message setup.

The next patch adds an additional case where the message header is
necessary.  So we want to do the g0 copy if inst->header_present is set,
rather than inst->texture_offset.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/vec4: Support arbitrarily large sampler state indices on Haswell+.

Like the scalar backend, we add an offset to the "Sampler State Pointer"
field to select a group of 16 samplers, then use the "Sampler Index"
field to select within that group.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
mesa: Bump MAX_TEXTURE_IMAGE_UNITS to 32.

This allows drivers to optionally support more than 16 texture units.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: Switch from BRW_MAX_TEX_UNIT to the actual limit.

BRW_MAX_TEX_UNIT is about to grow, but only Gen7+ will be able to
support the new larger value.  On older platforms, we don't want to
allocate the extra space - it would just be a waste.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Support 32 texture image units on Haswell+.

The Intel closed source OpenGL driver recently began supporting 32
texture image units on Haswell.  This makes the open source driver
support 32 as well.

Earlier generations don't have the message header field required to
support more than 16 sampler states, so we continue to advertise 16
there.

On Haswell, this causes us to advertise:
- GL_MAX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96
instead of the old values of 16, 16, and 48.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/blorp: introduce separate eu-emitter for blit compiler

Prepares for presenting blorp blit programs using FS IR that
allows EU-assembly generation using i965 glsl-compiler
backend (fs_generator).

v2: rebased on top of endif-jump counter fix (moving the
    added brw_set_uip_jip() into the emitter)

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>