mtd: nand: omap: Revert to using software ECC by default

[ Upstream commit 7d5929c1f34304ca5a970cfde8044053e56aa8c9 ]

For v3.12 and prior, 1-bit Hamming code ECC via software was the
default choice. Commit c66d039197e4 in v3.13 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.

This ECC layout change causes NAND filesystems created in v3.12
and prior to be unusable in v3.13 and later. So revert back to
using software ECC by default if an ECC scheme is not explicitely
specified.

This defect can be observed on the following boards during legacy boot

-omap3beagle
-omap3touchbook
-overo
-am3517crane
-devkit8000
-ldp
-3430sdp

Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: OMAP2+: GPMC: Support Software ECC scheme via DT

[ Upstream commit a3e83f05fbbf6c4994c658521a750bbd68bdf7a6 ]

For v3.14 and prior, 1-bit Hamming code ECC via software was the
default choice for some boards e.g. 3430sdp.
Commit ac65caf514ec in v3.15 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.

This ECC layout change causes NAND filesystems created in v3.14
and prior to be unusable in v3.15 and later. So don't mark "sw" scheme
as deperecated and support it.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: dts: omap3430-sdp: Revert to using software ECC for NAND

[ Upstream commit d5c1eb17ba052966debc4d9d103fc15740b541fa ]

For v3.14 and prior, 1-bit Hamming code ECC via software was used
for NAND on this board.
Commit c06c52701695 in v3.15 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.

This ECC layout change causes NAND filesystems created in v3.14
and prior to be unusable in v3.15 and later. So revert back to
using software ECC scheme.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
mfd: ti_am335x_tscadc: Fix TSC operation after ADC continouous mode

After enabling and disabling ADC continuous mode via sysfs, ts_print_raw
fails to return any data. This is because when ADC is configured for
continuous mode, it disables touch screen steps.These steps are not
re-enabled when ADC continuous mode is disabled. Therefore existing values
of REG_SE needs to be cached before enabling continuous mode and
disabling touch screen steps and enabling ADC steps. The cached value
are to be restored to REG_SE once ADC is disabled.

Fixes: 7ca6740cd1cd ("mfd: input: iio: ti_amm335x: Rework TSC/ADC synchronization")

Cc: stable@vger.kernel.org # v3.13+
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()

Simplify set_gpmc_timing_reg() and always print error message
if the requested timing cannot be achieved due to a too fast
GPMC functional clock, irrespective if whether DEBUG is defined
or not. This should help us debug timing configuration issues,
which were otherwise simply not being displayed in the kernel log.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child()

gpmc_cs_set_timings() returns non-zero if there was
an error while setting the GPMC timings. e.g. Timing was too
large to be accomodated with current GPMC clock frequency and available
timing range. Fail in this case, else we risk operating a NOR device
with non compliant timings.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices

Although RESET state of LIMITEDADDRESS bit in GPMC_CONFIG register
is 0 (i.e. A26-A11 enabled), faulty bootloaders might accidentally
set this bit. e.g. u-boot 2014.07 with CONFIG_NOR disabled.

Explicity disable LIMITEDADDRESS bit for non NAND devices so that
they can always work.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it

As per the OMAP reference manual [1], the Chip Select must be
disabled (i.e. CSVALID is 0) while configuring any of the
Chip select parameters.

[1] - 10.1.5.1 Chip-Select Base Address and Region Size Configuration
http://www.ti.com/lit/pdf/swpu177

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: dts: dra7-evm: Fix NAND GPMC timings

The nand timings were scaled down by 2 to account for
the 2x rate returned by clk_get_rate(gpmc_fclk).

As the clock data is now fixed by [1], revert back to actual
timings (i.e. scale them up by 2).

[1] - commit 863fab68f5384f8941c9b0b203675d4a9890fc54
    ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: dts: dra72-evm: Fix NAND GPMC timings

The nand timings were scaled down by 2 to account for
the 2x rate returned by clk_get_rate(gpmc_fclk).

As the clock data is now fixed by [1], revert back to actual
timings (i.e. scale them up by 2).

[1] - commit 863fab68f5384f8941c9b0b203675d4a9890fc54
    ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge branch 'connectivity-ti-linux-3.14.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-3.14.y

TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-3.14.y

* 'connectivity-ti-linux-3.14.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
  mfd: ti_am335x_tscadc: Fix TSC operation after ADC continouous mode
  ARM: dts: omap3430-sdp: Revert to using software ECC for NAND
  ARM: OMAP2+: GPMC: Support Software ECC scheme via DT
  mtd: nand: omap: Revert to using software ECC by default

Signed-off-by: Dan Murphy <DMurphy@ti.com>
Merge branch 'connectivity-ti-linux-3.14.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-3.14.y

TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-3.14.y

* 'connectivity-ti-linux-3.14.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
  ARM: dts: dra72-evm: Fix NAND GPMC timings
  ARM: dts: dra7-evm: Fix NAND GPMC timings
  ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it
  ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices
  ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child()
  ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()

Signed-off-by: Dan Murphy <DMurphy@ti.com>