Add support for MIPS r3 and r5.

2014-06-03  Andrew Bennett  <andrew.bennett@imgtec.com> 

	* config/mips/mips-cpus.def: Add mips32r3, mips32r5, mips64r3 and
	mips64r5.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_compute_frame_info): Changed if statement
	to use mips_isa_rev rather than ISA_MIPS32R2.
	* config/mips/mips.h (ISA_MIPS32R3): New define.
	(ISA_MIPS32R5): New define.
	(ISA_MIPS64R3): New define.
	(ISA_MIPS64R5): New define.
	(TARGET_CPU_CPP_BUILTINS): Added support for ISA_MIPS32R3, ISA_MIPS32R5,
	ISA_MIPS64R3 and ISA_MIPS64R5.
	(MIPS_ISA_LEVEL_SPEC): Added support for mips32r3, mips32r5, mips64r3
	and mips64r5.
	(MIPS_ISA_SYNCI_SPEC): Likewise.
	(ISA_HAS_64BIT_REGS): Added ISA_MIPS64R3 and ISA_MIPS64R5.
	(LINK_SPEC): Added mips32r3 and mips32r5.
	* config/mips/t-isa3264 (MULTILIB_MATCHES): Map mips32r3 and mips32r5
	to mips32r2; and mips64r3 and mips64r5 to mips64r2.
	* config/mips/t-mti-elf (MULTILIB_MATCHES): Likewise.
	* config/mips/t-mti-linux (MULTILIB_MATCHES): Likewise.
	* config/mips/t-sde (MULTILIB_MATCHES): Likewise.
	* config/mips/t-sdemtk (MULTILIB_MATCHES): New define.
	* doc/invoke.texi: Document mips32r3, mips32r5, mips64r3 and mips64r5.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211173 138bc75d-0d04-0410-961f-82ee72b054a4
Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.

        * config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
        New pattern.
        * config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
        (aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
        * config/aarch64/iterators.md (REVERSE): New iterator.
        (UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
        (rev_op): New int_attribute.
        * config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
        vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
        vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
        vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
        vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
        vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
        vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
        Replace temporary __asm__ with __builtin_shuffle.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211174 138bc75d-0d04-0410-961f-82ee72b054a4
Detect EXT patterns to vec_perm_const, use for EXT intrinsics.
(part 2, fix ICE at -O0)

	* config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle
	location == 0.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211177 138bc75d-0d04-0410-961f-82ee72b054a4
	PR c++/61020
	* varpool.c (ctor_for_folding): Handle uninitialized vtables.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211178 138bc75d-0d04-0410-961f-82ee72b054a4
	PR c++/60848
	* call.c (is_std_init_list): Check CLASSTYPE_TEMPLATE_INFO.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211179 138bc75d-0d04-0410-961f-82ee72b054a4
2014-06-03  Teresa Johnson  <tejohnson@google.com>

	* tree-sra.c (modify_function): Record caller nodes after rebuild.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211180 138bc75d-0d04-0410-961f-82ee72b054a4
[PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.h

	* gcc/config/aarch64/aarch64-builtins.c
	(aarch64_types_binop_uus_qualifiers,
	aarch64_types_shift_to_unsigned_qualifiers,
	aarch64_types_unsigned_shiftacc_qualifiers): Define.
	* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
	uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
	sqshlu_n, uqshl_n): Update qualifiers.
	* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
	vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
	vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
	vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
	vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
	vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
	vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
	vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
	vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
	vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
	vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
	vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
	vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
	vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
	vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
	vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
	vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
	vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
	vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
	vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
	vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
	vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
	vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
	vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
	vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
	vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
	vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211185 138bc75d-0d04-0410-961f-82ee72b054a4
[PATCH AArch64 2/2] Correct signedness of builtins, remove casts from arm_neon.h

	* gcc/config/aarch64/aarch64-builtins.c
	(aarch64_types_binop_ssu_qualifiers): New static data.
	(TYPES_BINOP_SSU): Define.
	* gcc/config/aarch64/aarch64-simd-builtins.def (suqadd, ushl, urshl,
	urshr_n, ushll_n): Use appropriate unsigned qualifiers.
	* gcc/config/aarch64/arm_neon.h (vrshl_u8, vrshl_u16, vrshl_u32,
	vrshl_u64, vrshlq_u8, vrshlq_u16, vrshlq_u32, vrshlq_u64, vrshld_u64,
	vrshr_n_u8, vrshr_n_u16, vrshr_n_u32, vrshr_n_u64, vrshrq_n_u8,
	vrshrq_n_u16, vrshrq_n_u32, vrshrq_n_u64, vrshrd_n_u64, vshll_n_u8,
	vshll_n_u16, vshll_n_u32, vuqadd_s8, vuqadd_s16, vuqadd_s32,
	vuqadd_s64, vuqaddq_s8, vuqaddq_s16, vuqaddq_s32, vuqaddq_s64,
	vuqaddb_s8, vuqaddh_s16, vuqadds_s32, vuqaddd_s64): Add signedness
	suffix to builtin function name, remove cast.
	(vshl_s8, vshl_s16, vshl_s32, vshl_s64, vshl_u8, vshl_u16, vshl_u32,
	vshl_u64, vshlq_s8, vshlq_s16, vshlq_s32, vshlq_s64, vshlq_u8,
	vshlq_u16, vshlq_u32, vshlq_u64, vshld_s64, vshld_u64): Remove cast.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211186 138bc75d-0d04-0410-961f-82ee72b054a4
	PR c++/60992
	* pt.c (tsubst_copy) [VAR_DECL]: Try lookup first.  Add a new
	variable to local_specializations.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211188 138bc75d-0d04-0410-961f-82ee72b054a4
	* config/avr/avr-mcus.def: Add new avr25 devices attiny441, attiny828
	and attiny841.
	* config/avr/avr-tables.opt: Regenerate.
	* config/avr/t-multilib: Regenerate.
	* doc/avr-mmcu.texi: Regenerate.

	* config/avr/avr-mcus.def (ata6616c): Add new avr25 device.
	(ata6617c, ata664251): Add new avr35 devices.
	(ata6612c): Add new avr4 device.
	(ata6613c, ata6614q): Add new avr5 devices.
	* config/avr/avr-tables.opt: Regenerate.
	* config/avr/t-multilib: Regenerate.
	* doc/avr-mmcu.texi: Regenerate.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211189 138bc75d-0d04-0410-961f-82ee72b054a4
	PR c/60439
	* doc/invoke.texi: Document -Wswitch-bool.
	* function.c (stack_protect_epilogue): Cast controlling expression of
	the switch to int.
	* gengtype.c (walk_type): Generate switch expression with its
	controlling expression cast to int.
c/
	* c-parser.c (c_parser_switch_statement): Pass explicit_cast_p to
	c_start_case.
	* c-tree.h (c_start_case): Update.
	* c-typeck.c (c_start_case): Add new boolean parameter.  Warn if
	switch condition has boolean value.
cp/
	* semantics.c (finish_switch_cond): Warn if switch condition has
	boolean value.
c-family/
	* c.opt (Wswitch-bool): New option.
testsuite/
	* c-c++-common/pr60439.c: New test.
	* g++.dg/eh/scope1.C (f4): Add dg-warning.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211194 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/cp
2014-06-03  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 1423
	PR c++/52174
	* call.c (standard_conversion): Convert nullptr to bool only
	in case of direct-initialization.
	(convert_like_real): Provide informative error message.

gcc/testsuite
2014-06-03  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 1423
	PR c++/52174
	* g++.dg/cpp0x/nullptr31.C: New.
	* g++.dg/cpp0x/sfinae-nullptr1.C: Likewise.
	* g++.dg/cpp0x/nullptr17.C: Update.

libstdc++-v3
2014-06-03  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 1423
	PR c++/52174
	* testsuite/20_util/is_assignable/value.cc: Update.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211195 138bc75d-0d04-0410-961f-82ee72b054a4
	* g++.dg/ext/mv14.C (dg-options): Add -march=x86-64.
	* g++.dg/ext/mv15.C (dg-options): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211196 138bc75d-0d04-0410-961f-82ee72b054a4