Swap qdr1 and qdr2 chips

On Dec 10, 2013, at 12:16 PM, Primiani, Rurik wrote:

> Set the QDR chip parameter of "transpose_1/qdr_transpose" to "qdr2" and the
> QDR chip parameter of "xengine/final_acc/dualsb_vacc/qdr_vacc/qdr2" to "qdr1"
> (perhaps rename it to "qdr1" to be consistent). I was looking at the layout
> of the chip in Plan Ahead the other day and I believe swapping these two QDRs
> will benefit timing.

Making these changes involved the following details:

The qdr_transpose block in mlib_devel only had qdr0 and qdr1 as options, so I
had to modify that block in the library to add qdr2 and qdr3 as options.  Then
updated the transpose_1/qdr_transpose block from the library, then (finally)
selected "qdr2".

Changed xengine/final_acc/dualsb_vacc/qdr_vacc/qdr2 to qdr1 both in name and in
the actual QDR chip specified.

Changed the name of the "qdr2_status" ports and registers to "qdr1_status".
This rippled all the way to changing the name of the software register
"xengine/final_acc/qdr2_status" to "xengine/final_acc/qdr1_status".  I don't
think this is a frequently used register, but any scripts that use the old name
will need to be updated to use the new name.
Add software registers for external sync stats

On Dec 10, 2013, at 12:16 PM, Primiani, Rurik wrote:

> Add two registers "sync/cnt0" and "sync/cnt1" (or something like that) with
> counters that count the posedges of signals "adcsync_0" and "adcsync_1"
> respectively. We had a problem the other day on the summit where one of the
> ROACH2 sync connectors broke and no HB was coming in.  The only symptom of
> this was sync misalignment on the board and I thought it would be nice to
> count the actual external syncs to see if they're arriving at all.

One sync is SOWF and the other is PPS.  They are software swappable.  I added
the following software registers (and requisite logic) after the software
swapping muxes:

sync/ext_sowf_cnt - Number of rising edges on external SOWF sync signal (mod
2**32).

sync/ext_sowf_period - Number of FPGA clock cycles between two most recent
external SOWF signals (mod 2**32).

sync/ext_pps_cnt - Number of rising edges on external 1PPS sync signal (mod
2**32).

sync/ext_pps_period - Number of FPGA clock cycles between two most recent
external 1PPS signals (mod 2**32).
Extend SOWF so that all X engines receive it

The mcount generator also generates the SOWF signal for the data packets.  This
generated SOWF signal was high for 128 cycles which corresponded to the first
packet sent out each interface for a Walsh Frame.  The first packet sent out
each interface is always destined for the ROACH2 with FID=0, so only that
ROACH2 would get packets with SOWF=1 in the header.

To fix this, the generated SOWF is now held high for 8 times longer so that the
first 8 packets sent out an interface for a Walsh Frame have SOWF=1 in the
header.  This will allow all 8 ROACH2s to receive SOWF=1 in the header of the
appropriate packets.
Add network/sync_count register

This counts the number of sync pulses sent to the X engines.  More
specifically, it counts the number of FPGA cycles for which the sync output
(from the network subsystem) is high.  The sync output is generated by an edge
detector.
Unignore sma_corr/bit_files/*.bof.gz files
Add sma_corr_2014_Jan_16_0340.bof.gz

This version added the network/sync_count register that counts sync pulses
being sent to the X engines.

WARNING: THIS BUILD FAILED TO MEET TIMING!!!

This build failed timing, so is not usable for production, but I think the
timing errors will affect only the data values and NOT the sync pulse timing,
so it might be useful for testing whether the X engines are getting sync pulses
at the expected rate.
Be smarter about SOWF receive buffering

The SOWF bit is asserted at t=0 for all FIDs when stored in the receive buffer.
Since SOWF becomes the X engine sync pulse, we must ensure that we output it
only once per Walsh frame (i.e. instead of once per FID per Walsh frame).
Additionally, we need to output it at the start of Walsh frame (i.e. with FID
0) even if we did not receive any FID 0 data.

This commit adds special buffering of the SOWF bit that is intended to
accomplish the above goals.
Change packet buffer readout control logic

The packet buffer readout control logic used to start reading from the packet
buffer when they had recevied half their capacity in packets.  This would be
fine when running with the full complement of ROACH2s, but when running with
half or a quarter of the ROACH2, this approach is flawed.

The new approach now starts reading from the packet buffers as soon as the
third of the four slots (i.e. the first slot of the second half) is written to.
This will allow start the readout at the apropriate time even when runninf with
fewer than the full complement of ROACH2s.
Add sma_corr_2014_Jan_18_1927.bof.gz

This BOF file has fixes to address the antenna mis-labeling bug (that is
suspected to be caused by extraneous SOWF/sync pulses being sent to the X
engines).  It also contains changes to address a weakness in the receive buffer
readout control logic when running with fewer than the full complement of
ROACH2s.