util/primconvert: pass index bias through

The index_bias (aka base_vertex) applies to the downstream draw just as
much, since the actual index values are never modified.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
util/primconvert: support instanced rendering

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
util/primconvert: take ib offset into account

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
util/primconvert: Avoid point arithmetic; apply offset on all cases.

Matches what u_vbuf_get_minmax_index() does.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
mesa: Ensure stack is realigned on x86.

Nowadays GCC assumes stack pointer is 16-byte aligned even on 32-bits,
but that is an assumption OpenGL drivers (or any dynamic library for
that matter) can't afford to make as there are many closed- and open-
source application binaries out there that only assume 4-byte stack
alignment.

This fix uses force_align_arg_pointer GCC attribute, and is only a
stop-gap measure.

The right fix would be to pass -mstackrealign or
-mincoming-stack-boundary=2 to all source fails that use any -msse*
option, as there is no way to guarantee if/when GCC will decide to spill
SSE registers to the stack.

https://bugs.freedesktop.org/show_bug.cgi?id=86788

Reviewed-by: Brian Paul <brianp@vmware.com>
glsl: Optimize scalar all_equal/any_nequal into equal/nequal.

Cuts an instruction from two shaders in Tesseract, by allowing the
(x+y) cmp 0 -> x cmp -y optimization to take place.

instructions in affected programs:     1198 -> 1194 (-0.33%)

Reviewed-by: Eric Anholt <eric@anholt.net>
i965/vec4: Allow CSE on uniform-vec4 expansion MOVs.

Three source instructions cannot directly source a packed vec4 (<0,4,1>
regioning) like vec4 uniforms, so we emit a MOV that expands the vec4 to
both halves of a register.

If these uniform values are used by multiple three-source instructions,
we'll emit multiple expansion moves, which we cannot combine in CSE
(because CSE emits moves itself).

So emit a virtual instruction that we can CSE.

Sometimes we demote a uniform to to a pull constant after emitting an
expansion move for it. In that case, recognize in opt_algebraic that if
the .file of the new instruction is GRF then it's just a real move that
we can copy propagate and such.

total instructions in shared programs: 5822418 -> 5812335 (-0.17%)
instructions in affected programs:     351841 -> 341758 (-2.87%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vec4: Don't DCE flag-writing insts because dest was unused.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/fs: Add a negate() function.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965: Change the type of booleans to D.

This is a revert of commit 4656c14e ("i965/fs: Change the type of
booleans to UD and emit correct immediates") plus some small additional
fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD
to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000
as UD and as a literal it's more recognizable than 1065353216.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965: Use ~0 to represent true on all generations.

Jason realized that we could fix the result of the CMP instruction on
Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
backend before use, rather than when the bool was created. The FS does
this and it saves some unnecessary resolves.

On Ironlake:

total instructions in shared programs: 4289762 -> 4287277 (-0.06%)
instructions in affected programs:     619430 -> 616945 (-0.40%)

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/fs: Make brw_reg_from_fs_reg static and remove prototype.

And move it above its first use in brw_fs_generator.cpp.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/fs: Move brw_file_from_reg() higher in the file.

This was supposed to be part of the previous commit.
vc4: Add a debug flag for waiting for sync on submit.

This is nice when you're tracking down which command list is hanging the
GPU.
vc4: Allow dead code elimination of color reads.

This might happen if the blending functions are set up to not actually use
the destination color/alpha, for example.
vc4: Refuse to merge two ops that both access shared functions.

Avoids assertion failures in vc4_qpu_validate.c if we happen to find the
right set of operations available.
vc4: Fix inverted priority of instructions for QPU scheduling.

We were scheduling TLB operations as early as possible, and texture setup
as late as possible.  When I introduced prioritization, I visually
inspected that an independent operation got moved above texture results
collection, which tricked me into thinking it was working (but it was just
because texture setup was being pushed late).

total instructions in shared programs: 57651 -> 57486 (-0.29%)
instructions in affected programs:     18532 -> 18367 (-0.89%)
vc4: Add separate write-after-read dependency tracking for pairing.

If an operation is the last one to read a register, the instruction
containing it can also include the op that has the next write to that
register.

total instructions in shared programs: 57486 -> 56995 (-0.85%)
instructions in affected programs:     43004 -> 42513 (-1.14%)
i965/gs: Avoid DW * DW mul

The GS has an interesting use for mul. Because the GS can emit multiple
vertices per input vertex, and it also has a unique count at the top of the URB
payload, the GS unit needs to be able to dynamically specify URB write offsets
(relative to the global offset). The documentation in the function has a very
good explanation from Paul on the mechanics.

This fixes around 2000 piglit tests on BSW.

v2:
Reworded commit message (Ben) no mention of CHV (Matt)
Change SHRT_MAX to USHRT_MAX (Ken, and Matt)
Update comment in code to reflect the use of UW (Ben)
Add Gen7+ assertion for the relevant GS code, since it won't work on Gen6- (Ken)
Drop the bogus hunk in emit_control_data_bits() (Ken)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84777 (with many dupes)
Cc: "10.4 10.3 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
configure.ac: Replace contraction to fix syntax highlighting.