refactoring connection into explicit/implicit connectors
corrected bug in ExplicitConnector, refactoring a bit
could be improved, probably by decorrelating checks and connection
creation. It would make the code much more readable I think. A good way
to do this would be first building a list of pairs of endpoints
(matching target with source endpoint), then checking type+interface,
then creating connections, finally removing ports from port map.
reflected a change in FIFOs port names in VHDL library
corrected sim package for VHDL.
The value of a port must not change when 'send' goes down. This matches
the behavior of what we generate for VHDL and Verilog. Not resetting the
value whenever 'send' goes down is necessary for proper cross domain
crossing, it makes more sense and also saves space.