ec2 scripts: optionally support small instances

There are 2 types of HVM AMIs on Amazon:

1. Windows based that support all instances types
2. Linux based that support instances larger than medium only

Linux based AMIs suit OSv better because their default seciurity
policy exactly fits OSv model (SSH access) and doesn't require
reconfiguration.

Windows based AMIs require default security policy reconfiguration
in order to allow SSH access but from other hand allow running OSv
on free-tier eligible micro instances which is good for enthusiasts
and initial evaluations.

In order to support both options this patch extends release scripts
with ability to choose between Windows and Linux based templates
during AMIs creation.

Signed-off-by: Dmitry Fleytman <dmitry@daynix.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>
apps: update for netperf jenkins integration

Signed-off-by: Avi Kivity <avi@cloudius-systems.com>
ahci: Relax _cmd_table and _recv_fis alignment

AHCI spec says cmd_table need to be aligned to 128 bytes, respect it.

AHCI spec does not specify the alignment requirement of _cmd_list and
_recv_fis. To be safe, we align to their size, i.e. 1024 and 256 bytes.

This fixes the issue reported by Roman Shaposhnik.

   $ capstan run -p vbox
   Created instance: i1398297574
   OSv v0.07
   Assertion failed: !(reinterpret_cast<uintptr_t>(ret) & (align - 1))
   (/home/penberg/osv/core/mempool.cc: alloc_phys_contiguous_aligned:
   1378)

   [backtrace]
   0x398316 <memory::alloc_phys_contiguous_aligned(unsigned long,
   unsigned long)+214>
   0x3542bb <ahci::port::setup()+283>
   0x3549ae <ahci::port::port(unsigned int, ahci::hba*)+142>
   0x354a5f <ahci::hba::scan()+111>
   0x354d34 <ahci::hba::hba(pci::device&)+148>
   0x354e07 <ahci::hba::probe(hw::hw_device*)+119>
   0x33e65c
   <hw::driver_manager::register_driver(std::function<hw::hw_driver*
   (hw::hw_device*)>)+188>
   0x33c8c3 <hw::device_manager::for_each_device(std::function<void
   (hw::hw_device*)>)+51>
   0x33e3de <hw::driver_manager::load_all()+78>
   0x20edf5 <do_main_thread(void*)+629>
   0x3ff0a5 <sync+69>
   0x3a3eaa <thread_main_c+26>
   0x361585 <thread_main+7>

Signed-off-by: Asias He <asias@cloudius-systems.com>
Signed-off-by: Avi Kivity <avi@cloudius-systems.com>
aarch64: mmu: distinguish between device and normal memory

we need to do that because load/store instructions
behave differently with Device-nGnRnE memory.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: gic: implement GICv2

implement simple GIC class for interacting with
the GIC distributor and CPU interface.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: exceptions: implement interrupt table

implement a simple interrupt table to register
interrupt IDs and handlers. Map the GIC so it
can be initialized by the table constructor.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: smp: prepare GIC initialization per cpu

arch::init_on_cpu should initialize the gic cpu interface,
but not for the boot CPU, for which this has already been
done.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: implement basic General Timers infrastructure

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>