Implement more aarch64 vector insns:
{S,U}{MIN,MAX}  Vd.T, Vn.T, Vm.T (8bitx16lane variants)
{S,U}{MIN,MAX}V Vd.T, Vn.T, Vm.T (8bitx16lane variants)
FMOV (vector, immediate)
MOVI (vector, immediate)
FABS (vector)
FNEG (vector)
FMLA (vector)
FMLS (vector)
{AND,BIC,ORR,ORN} (vector)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2815 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix the ppc32 special-instruction magic sequence so it really does
preserve the value of r0, as claimed.  Fixes #278808 (VEX side).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2816 8f6e269a-dfd6-0310-a8e1-e2731360e62c