Triple: Add AMDHSA operating system type

This operating system type represents the AMD HSA runtime,
and will be required by the R600 backend in order to generate
correct code for this runtime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223124 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223125 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: make register block rules apply to vector types too.

The blocking code originated in ARM, which is more aggressive about casting
types to a canonical representative before doing anything else, so I missed out
most vector HFAs and broke the ABI. This should fix it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223126 91177308-0d34-0410-b5e6-96231b3b80d8
fix typo in comment


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223127 91177308-0d34-0410-b5e6-96231b3b80d8