defconfig: Update

Signed-off-by: Kostas K <mpokwsths@gmail.com>
clock-mdss-8974: Switch HDMI clocks to use the new PLL implementation

This change cleans up the HDMI VCO/PLL implementation. It implements
the HDMI VCO clock and uses generic div and mux clocks to align to
the HDMI PLL architecture.

CRs-Fixed: 456315
Change-Id: I19ef344aafc954935cd6d236f3725bf168658ec9
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: clock-mdss-8974: Enable AHB clock before register access

Enable the MDSS AHB clock for proper HDMI PHY PLL register
access. Disable the MDSS AHB clock after register access.

Change-Id: Ice8e723333f3c041bc1cffa2ebc8d7d40a8817d2
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: clock-mdss-8974: Proper hdmi set rate

Do not call set rate if the rate is zero. Reset the flag which sets
the rate on cable disconnect so that next cable connect can set the
rate again.

Change-Id: Ieb8eed3760c4b285182ae47d732352771d13b020
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: clock-mdss-8974: Dynamic HDMI PHY-PLL configuration

Implement the  HDMI PHY PLL calculator to dynamically configure the
HDMI PLL VCO to any supported pixel rate within the supported range.

Change-Id: I5665509aeaf54132ae711e3c4c9be542b25b8241
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: clock-mdss: correct check for MDSS GDSC status

MDSS GDSC may be always on but clock is off in reset state.
Therefore, the correct way to check GDSC status is read both
gdsc enable bit and the clock reset bit. This change is
necessary to prevent potential crashes that may occur if
MDSS registers are accessed when MDSS GDSC is not enabled.

Change-Id: I501450beed3ea798329b34b96f2966cfefc901c2
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
msm: clock-mdss: Update PLL enable sequence for MSM8226

Update the PLL enable sequence to address PLL lock failures
seen sporadically on MSM8226.

Change-Id: I44c42f92d92d20ca8dece1ed516a9fa8db5eda44
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: clock-mdss: Do not toggle lock detect during handoff

If continuous splash screen feature is enabled, then the DSI
clocks are left on in the bootloader. When the kernel boots
up, te DSI PLL lock status is checked in order to determine
whether these clocks should be handed off or not. Ensure that
the lock detect register is not toggled at this time to avoid
any blinks in the display.

Change-Id: Ica8c42e260d9b3ceffda885b1942fab945f60c86
CRs-Fixed: 506037
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: Update dynamic HDMI clock API usage

Change-Id: Iaf73517bd41a8656a72be2e1d8768c1cd17b6082
msm: mdss: Fix race condition for vsync irq enable/disable

Disable and enable of vsync happens in separate thread, which
may lead to a race condition where enable/disable may
happen at the same time and resulting irq in disable state.
Add lock to properly synchronize the enabling/disabling
of vsync interrupts to fix race condition.

Change-Id: Ib52bea5ca7a3612c866a4a962f09725a77e40563
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
msm: mdss: set vsync clock rate

Vsync clock rate is not set when vsync clock is enabled.
This cause command mode TE logic not works.

Change-Id: Ibf7dd07e53b2cd76ef30f13133368000c79ae149
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm: mdss: Configure minimum voltage for CX power rail

For smart panels, we observe abnormal waveforms
and unexpected voltage spikes on DSI data lanes
when the cx power rail goes to minimum voltage.
Vote for the cx regulator in mdp driver and control
the voltage to avoid frame shifting.

Change-Id: I7ec9e29a4972373775406fa29a5037fd43fef315
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
msm: mdss: Add battery FET regulator usage

During idle power-collapse using smart-panel, when PMIC chip goes to
sleep, it puts battery FET (batfet) to low power mode (LPM) which allows
less than 100mA current to be drawn. Since smart-panel is in self-refresh
mode, it can still draw more than 100mA current causing PMIC and MSM
reset. To fix this issue, batfet has to be kept in high power mode (HPM).
In order to keep batfet in HPM, display driver enables batfet regulator
whenever display panel is on.

Change-Id: I2f3d9f20fcf86b3147ac7396d56f93bfc08377c7
Signed-off-by: Shalabh Jain <shalabhj@codeaurora.org>
msm: mdss: Detach mdss iommu on static screen

Detach mdss iommu on static screen and re-attach
on next commit to allow full power collapse of MDSS.
IOMMU driver keeps its vote for bus bandwidth for as
long as the MDP driver is attached to the IOMMU.
When MDP detaches from the IOMMU, IOMMU driver will
remove its vote for bus bandwidth.

Change-Id: I1e5c5c50bc157c3ebfc63e198e4608dad820a288
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
msm: Add NULL pointer check before ion cache operation

If the ion buffer is of size zero, NULL pointer
dereferencing may take place. Avoid it by adding
a check before function call.

Change-Id: If6c19a94f70f3658c5323a0742399ec977944da7
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
msm: mdss: Fix slower clocks during histogram and hist LUT accesses

Slower CNOC clock rates cause histogram and hist LUT access to take
longer time. Fix CNOC clock configuration at optimum rate in order
to avoid slow accesses to histogram and hist LUT.

Change-Id: I066bae9fd0b4261b71248cffea65d8949ff6aae2
Signed-off-by: Ping Li <quicpingli@codeaurora.org>
msm: mdss: Revert changes for separating out PP flushes from commits

MDP flush behavior on MSM8974 needs to have single flush in given vsync
cycle, more than one flushes in same vsync cycle can cause unexpected
behavior such as blank screens, incorrect frame updates on LCD or some
visual artifacts. Currently post processing and frame updates have
independent flush mechanisms which in certain cases can cause visual
artifacts or blank screen. So revert changes to independently flush
MDP registers so that post processing piggybacks on flushes for frame
updates.

CRs-Fixed: 494856
Change-Id: Iaa0f6f123487f57abb1b56f7d0946fa3abfe3058
Signed-off-by: Ping Li <quicpingli@codeaurora.org>
msm: mdss: Control histogram intr and clk in suspend cases

Histogram interrupts, and clocks used to handle interrupts, need to be
enabled in sync with histogram requests. To ensure that these interrupts
and clocks are disabled when screen is suspended or not updating, a control
structure is introduced that allows for these resources to be gated by
specifying transitions from when they should and should not be active.

CRs-Fixed: 568049
Change-Id: I77a50085ee38de597092c273c7ce9974c7bb29c3
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
msm: mdss: Reserve framebuffer memory for the splash screen

Reserve memory for the framebuffer in the HLOS partition that
would be used to display splash screen in the bootloader as
well as the initial stages of the kernel bootup. This avoids
copying splash screen memory to a local buffer in the kernel.
The reserved memory would be freed when the first real update
comes in from the userspace.

Change-Id: I7dc256f8ffd69c24e56ac10ed57e37d96c8c9a2f
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: mdss: initialize pipe to NULL

Initialize the pipe pointer to NULL.
So that even if the selection of pipe from pipe-pool
fails, the function returns NULL instead of an
uninitialized value.

Change-Id: Ib04c0a983cba6ffe9532862bcaf516877e49746a
CRs-Fixed: 524466
Signed-off-by: Manoj Rao <manojraj@codeaurora.org>