[FastISel][AArch64] Fix simplify address when the address comes from a shift.

When the address comes directly from a shift instruction then the address
computation cannot be folded into the memory instruction, because the zero
register is not available as a base register. Simplify addess needs to emit the
shift instruction and use the result as base register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216621 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Fix a comment in my previous commit (r216617).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216622 91177308-0d34-0410-b5e6-96231b3b80d8
Use local variable in visitFADD. No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216623 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid zero length memset error

Adding a check on buffer lenght to avoid a __warn_memset_zero_len
warning on GCC 4.8.2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216624 91177308-0d34-0410-b5e6-96231b3b80d8