buildme.sh: switch to arm-linux-gnueabihf-4.9

Signed-off-by: Hieu Phan <aznrice2k4@gmail.com>
ARM: mm: implement LoUIS API for cache maintenance ops

ARM v7 architecture introduced the concept of cache levels and related
control registers. New processors like A7 and A15 embed an L2 unified cache
controller that becomes part of the cache level hierarchy. Some operations in
the kernel like cpu_suspend and __cpu_disable do not require a flush of the
entire cache hierarchy to DRAM but just the cache levels belonging to the
Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
correspond to L1.

The current cache flushing API used in cpu_suspend and __cpu_disable,
flush_cache_all(), ends up flushing the whole cache hierarchy since for
v7 it cleans and invalidates all cache levels up to Level of Coherency
(LoC) which cripples system performance when used in hot paths like hotplug
and cpuidle.

Therefore a new kernel cache maintenance API must be added to cope with
latest ARM system requirements.

This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.

This function cleans and invalidates all data cache levels up to the
Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
cache for processors that support it (> v7).

This patch also creates an alias of the cache LoUIS function to flush_kern_all
for all processor versions prior to v7, so that the current cache flushing
behaviour is unchanged for those processors.

v7 cache maintenance code implements a cache LoUIS function that cleans and
invalidates the D-cache up to LoUIS and invalidates the I-cache, according
to the new API.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Change-Id: I561c3b187b5b87b25de07ea82a4ef73a42761e27
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
ARM: kernel: update cpu_suspend code to use cache LoUIS operations

In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.

When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced cache LoUIS function.

The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.

outer_cache management remains unchanged.

Change-Id: Id5a6d34d55d1b0a5ef112cafc3ad21c0da4b0b84
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
drivers/input/touchscreen/ektf3k: auto retry 10 times on i2c reads
The i2c devices we are connecting to may not be ready yet, or just
busy. Retry with a 10ms pause in order to still obtain i2c data.
This improves overall i2c data robustness

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers/input/touchscreen/ektf3k: we only have 1 msg, so don't define 2

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers/input/touchscreen/ektf3k: we don't need to define a pointer for a ONE TIME USE! Clean up.

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: This is a oneshot irq

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: use threaded interrupt

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: use high-priority workqueue (+unbound, +rescuer, +mt)

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: This irq is used for polling

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: re-enable elan sysfs (android_touch)

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: if we recieve a malformed packet and it matched the GND issue, release all touches

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: add two more GND issue malformed packets

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: increase hw_reset delay

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: move touch release to separate workqueue

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers: touchscreen: elan: add additional packet

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers/input/touchscreen/ektf3k: for what do we need the touchscreen data? Clean up.

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers/input/touchscreen/ektf3k: remove comment as well, this will never be used again.

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers/input/touchscreen/ektf3k: rewrite i2c msg definition, the right way.

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>
drivers/input/touchscreen/ektf3k: auto retry 10 times on i2c reads
The i2c devices we are connecting to may not be ready yet, or just
busy. Retry with a 10ms pause in order to still obtain i2c data.
This improves overall i2c data robustness

Signed-off-by: Dennis Rassmann <showp1984@gmail.com>