mor1kx-defines: whitespace cleanup
mor1kx v1.0
cappuccino/lsu: simplify lsu_except_dbus_o
dcache: enable RAM bypass registers

This still required for the case where several < word writes
are written into the same word with no clock cycles between them.
cappuccino/lsu: remove tangling dc_cache_inhibit wire

The real wire is called dmmu_cache_inhibit
cappuccino/lsu: add store buffer

This pretty large patch adds a store buffer to cappuccinos lsu.
It's a very simple and naive one, where all stores are done into
a fifo. As long as the fifo is not full, execution are not
stalled until a load operation is performed.
There is no logic to check if the incoming load is in the
store buffer, the pipeline is unconditionally stalled
until the FIFO is empty.

This also moves all write related bus logic to the lsu,
i.e. the cache do not perform any bus operation related
to writes.

A bit of special handling is required to get the right offending
PC when a bus error happens for a store.
Since the pipeline isn't stalled, we need to save the right epcr
into the store buffer in order to match the PC to the store that
caused the bus error.
And also because the pipeline isn't stalled, instructions after the
offending store will have time to execute before the execution happens.
This is a change in behaviour from all other or1k implementations,
but not really against the arch spec.
A data bus error exception is anyways a "game over" situation,
so as long as you provide the user with the important information
of which address caused the error and at which PC did it happen,
it should be fine.
cappuccino/ctrl: fix stepping through mispredicted branches

When a mispredicted branch is stepped through, the branch target
have to be updated when the correct target is available.
cappuccino/fetch: initialize imem_err during reset

Without this, during simulations, ibus_adr_o is undefined
after reset is released. This undefined state can lead
to an undefined state on ibus_err_i and we are stuck in
this state.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
icache: reorganize OPTION_ICACHE_WAYS == 2 guard

When OPTION_ICACHE_WAYS == 1, code inside the
OPTION_ICACHE_WAYS == 2 guard contains references to out of
boundary indecies in vectors.
icarus can figure out that this code is not used, if the
OPTION_ICACHE_WAYS == 2 statement is on its own.
There are still problems with verilator, but that needs
a lot more work to fix.
update version number to v2.0

The version numbering policies are still a bit in flux,
but consensus from current discussions are that at least
master branch (development branch) should have a major
number one greater than the current release branch.
import mor1kx_monitor from mor1kx-dev-env

This file is useful for other verification set-ups than mor1kx-dev-env,
by adding it to the mor1kx project we can provide them with the file
without the overhead of acquring the whole mor1kx-dev-env.
cappuccino/fetch: wait out non-cache accesses

When an icache invalidate occur, the icache is muxed away from
ibus and the ongoing fetch is fetched from memory instead of cache.
This access have to finish before we can switch back to fetching
from cache.
cappuccino/lsu: initialize dbus_err on reset
cappuccino/lsu: set dbus_adr to zero when in IDLE state

When running in simulations an uninitialized dbus_adr would
cause X'es to propagate out on the bus.
Since bus arbiters might calculate bus errors from the
address, this could cause X'es to come back on dbus_err_i.
DCache: Non-disrupting invalidation

On the edge of an invalidation request the cache started one
invalidation of the respective tag. By permanently acknowledging the
SPR requests, this had to happen immediately which might corrupt other
processing. Furthermore the edge triggering is not correct as two
succeeding invalidations happen without a low cycle of the spr bus
strobe signal.

The new implementation simply always acknowledges SPR requests while
the invalidation can take place, which is during idle and
invalidation. In all other cases the operation is delayed until the
state machine returns to IDLE. When an invalidation lasts longer, the
respective tag is repeatedly cleared, which is no problem.

Finally, the state machine has been reordered without breaking the
functionality, but for a clear code layout (not overwriting sequential
assignments) and readability.
cappuccino/ctrl: only signal stepped_into_delay_slot when stepping

Otherwise spr_npc will contain the wrong value (last branch dest)
after all delay slots.
bus_if_avalon: remove vector size from OPTION_AVALON_BURST_LENGTH

Older versions of icarus doesn't support sized parameters.
Older versions of icarus doesn't support always @* with empty sensitivity list.

Please see http://sourceforge.net/p/iverilog/bugs/864/ for more info.
cappuccino/ctrl: add support for sw breakpoints

This essentially is a direct copy from what espresso does in its
ctrl module.
Same with commit 7d190bf. Make sure the rtl in espresso/prontoespresso is compatible with older version of icarus.