Added AVRAsmBackend and AVRELFObjectWriter
Added AVRMCCodeEmitter
Merge branch 'avr-support' into avr-obj-support
[AVR] Further progress on ELF support
[AVR] Specified binary sizes of instructions
[AVR] Fixed segmentation fault and added LE and BE AvrAsmBackend
[AVR] Fixed endian issue with AVRCodeEmitter

Outputted code had the byte order swapped.
[AVR] Removed code from AVRMCCodeEmitter
[AVR] Set HWEncoding for registers in AVRRegisterInfo.td

Before this, all register encodings were assumed to be zero, and so every register access would read or write to r0.
[AVR] Fixed AVR `cli` and `sli` instructions

They were encoded as `Pseudo` instructions which don't exist physically. Obviously this is wrong because cli and sli are real instructions.
[AVR] Cleaned up AVRInstrFormats.td and AVRInstrInfo.td
[AVR] Documented ST(D) instructions
[AVR] Implemented code generation for STD instruction

This is a horrible, horrible hack.

Also made Pseudo instructions emit 0xBEEF values instead of NOPs.
This way it is more obvious that there is an error.
[AVR] Fixed binary encoding of ADIW/SDIW instructions.

Previously the instructions would use the register number as the immediate.

Closes #13
[AVR] Removed Pseudo instruction HWEncoding

Setting emitted pseudo instructions to 0xBEEF doesn't help when
it is a valid instruction.
[AVR] Fixed various compiler warnings.

Closes #4.
[AVR] Implemented some support for the encoding of branch instructions
[AVR] Implemented fixups, added BRNE support
[AVR] Set the isPseudo bit for the Pseudo instruction format
Merge branch 'avr-obj-support' into avr-support