test: only core 0 writes, tighter memory test bounds for 1 MB and 16 cores
test: fix merge conflicts
test: only one Finished
simulator: Quick fix for load delay slot check.
simulator: fixed disabling of interrupts for ISRs
simulator: check for load hazards in MW stage instead of in IF stage
hardware: Make interrupts work with non-delayed CFL instructions.
simulator: Applied Wolfgang's patch to delay interrupts for all CFL instructions